mb/google/guybrush: Add helpers for cbi fw_config settings

Turn on CBI and add helper functions for determining the board
configuration from the firmware config settings in CBI.

BUG=b:187316460
TEST=Built

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2021-05-20 16:06:13 -06:00 committed by Martin Roth
parent dac1f66c6c
commit 57bc814ea1
5 changed files with 32 additions and 8 deletions

View File

@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
select ELOG
select ELOG_GSMI
select FW_CONFIG
select FW_CONFIG_SOURCE_CHROMEEC_CBI
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select HAVE_ACPI_RESUME
select HAVE_EM100_SUPPORT

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@ -1,9 +1,11 @@
bootblock-y += gpio.c
bootblock-y += helpers.c
romstage-y += helpers.c
romstage-y += tpm_tis.c
ramstage-y += gpio.c
ramstage-y += helpers.c
ramstage-y += tpm_tis.c
verstage-y += gpio.c

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@ -2,11 +2,20 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <fw_config.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
bool variant_has_fpmcu(void)
static bool variant_has_device_enabled(const struct device_path *device_path, size_t path_length)
{
const struct device *dev =
find_dev_nested_path(all_devices->link_list, device_path, path_length);
return is_dev_enabled(dev);
}
__weak bool variant_has_fpmcu(void)
{
DEVTREE_CONST struct device *mmio_dev = NULL;
static const struct device_path fpmcu_path[] = {
{
.type = DEVICE_PATH_MMIO,
@ -18,11 +27,18 @@ bool variant_has_fpmcu(void)
.generic.subid = 0
},
};
mmio_dev = find_dev_nested_path(
all_devices->link_list, fpmcu_path, ARRAY_SIZE(fpmcu_path));
if (mmio_dev == NULL)
return false;
return mmio_dev->enabled;
return variant_has_device_enabled(fpmcu_path, ARRAY_SIZE(fpmcu_path));
}
__weak bool variant_has_pcie_wwan(void)
{
static const struct device_path pcie_wwan_path[] = {
{
.type = DEVICE_PATH_PCI,
.pci.devfn = PCIE_GPP_2_2_DEVFN,
},
};
return variant_has_device_enabled(pcie_wwan_path, ARRAY_SIZE(pcie_wwan_path));
}

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@ -28,4 +28,6 @@ void variant_fpmcu_reset(void);
bool variant_has_fpmcu(void);
bool variant_has_pcie_wwan(void);
#endif /* __BASEBOARD_VARIANTS_H__ */

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@ -33,6 +33,9 @@ end
chip soc/amd/cezanne
device domain 0 on
device ref gpp_bridge_2 on
probe WWAN WWAN_FM350GL
end # WWAN
end # domain
register "slow_ppt_limit_mW" = "25000"