soc/intel/common/sgx: use SOC specific API to get PRMRR base and mask
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask. Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21246 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -21,6 +21,7 @@
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#include <intelblocks/mp_init.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/sgx.h>
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#include <intelblocks/systemagent.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include <string.h>
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@ -62,33 +63,50 @@ static int is_sgx_supported(void)
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void prmrr_core_configure(void)
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{
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msr_t prmrr_base;
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msr_t prmrr_mask;
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union {
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uint64_t data64;
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struct {
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uint32_t lo;
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uint32_t hi;
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} data32;
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} prmrr_base, prmrr_mask;
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msr_t msr;
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if (!soc_sgx_enabled() || !is_sgx_supported())
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return;
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/* PRMRR base and mask are read from the UNCORE PRMRR MSRs
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* that are already set in FSP-M. */
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prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
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prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR);
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if (!prmrr_base.lo) {
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printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n");
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return;
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}
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msr = rdmsr(PRMRR_PHYS_MASK_MSR);
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/* If it is locked don't attempt to write PRMRR MSRs. */
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if (msr.lo & PRMRR_PHYS_MASK_LOCK)
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return;
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/* Program core PRMRR MSRs */
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prmrr_base.lo |= MTRR_TYPE_WRBACK; /* cache writeback mem attrib */
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wrmsr(PRMRR_PHYS_BASE_MSR, prmrr_base);
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prmrr_mask.lo &= ~PRMRR_PHYS_MASK_VALID; /* Do not set the valid bit */
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prmrr_mask.lo |= PRMRR_PHYS_MASK_LOCK; /* Lock it */
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wrmsr(PRMRR_PHYS_MASK_MSR, prmrr_mask);
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/* PRMRR base and mask are read from the UNCORE PRMRR MSRs
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* that are already set in FSP-M. */
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if (soc_get_uncore_prmmr_base_and_mask(&prmrr_base.data64,
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&prmrr_mask.data64) < 0) {
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printk(BIOS_ERR, "SGX: Failed to get PRMRR base and mask\n");
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return;
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}
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if (!prmrr_base.data32.lo) {
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printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n");
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return;
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}
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printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64);
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printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64);
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/* Program core PRMRR MSRs.
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* - Set cache writeback mem attrib in PRMRR base MSR
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* - Clear the valid bit in PRMRR mask MSR
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* - Lock PRMRR MASK MSR */
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prmrr_base.data32.lo |= MTRR_TYPE_WRBACK;
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wrmsr(PRMRR_PHYS_BASE_MSR, (msr_t) {.lo = prmrr_base.data32.lo,
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.hi = prmrr_base.data32.hi});
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prmrr_mask.data32.lo &= ~PRMRR_PHYS_MASK_VALID;
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prmrr_mask.data32.lo |= PRMRR_PHYS_MASK_LOCK;
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wrmsr(PRMRR_PHYS_MASK_MSR, (msr_t) {.lo = prmrr_mask.data32.lo,
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.hi = prmrr_mask.data32.hi});
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}
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static int is_prmrr_set(void)
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