sb/amb/rs780: Get rid of device_t
By mistake this was forgotten from previous commit touching the same directory. Change-Id: I23e3e579ccbcb8a251cdde11215ec171b78b7159 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26494 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
219bacccb5
commit
57d71c8278
|
@ -44,10 +44,10 @@ PCIE_CFG AtiPcieCfg = {
|
|||
0 /* GppPwr */
|
||||
};
|
||||
|
||||
static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
|
||||
static void ValidatePortEn(device_t nb_dev);
|
||||
static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port);
|
||||
static void ValidatePortEn(struct device *nb_dev);
|
||||
|
||||
static void ValidatePortEn(device_t nb_dev)
|
||||
static void ValidatePortEn(struct device *nb_dev)
|
||||
{
|
||||
}
|
||||
|
||||
|
@ -55,7 +55,7 @@ static void ValidatePortEn(device_t nb_dev)
|
|||
* Compliant with CIM_33's PCIEPowerOffGppPorts
|
||||
* Power off unused GPP lines
|
||||
*****************************************************************/
|
||||
static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
|
||||
static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u32 reg;
|
||||
u16 state_save;
|
||||
|
@ -105,7 +105,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
|
|||
|
||||
/**********************************************************************
|
||||
**********************************************************************/
|
||||
static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
|
||||
static void switching_gppsb_configurations(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
|
@ -177,7 +177,7 @@ static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
|
|||
} while (reg & VC_NEGOTIATION_PENDING);
|
||||
}
|
||||
|
||||
static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
|
||||
static void switching_gpp_configurations(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
|
@ -202,7 +202,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
|
|||
* The rs780 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
|
||||
* Space to a 256MB range within the first 4GB of addressable memory.
|
||||
*****************************************************************/
|
||||
void enable_pcie_bar3(device_t nb_dev)
|
||||
void enable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
|
||||
|
@ -218,7 +218,7 @@ void enable_pcie_bar3(device_t nb_dev)
|
|||
* We should disable bar3 when we want to exit rs780_enable, because bar3 will be
|
||||
* remapped in set_resource later.
|
||||
*****************************************************************/
|
||||
void disable_pcie_bar3(device_t nb_dev)
|
||||
void disable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
|
||||
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
|
||||
|
@ -236,7 +236,7 @@ void disable_pcie_bar3(device_t nb_dev)
|
|||
* port:
|
||||
* p2p bridge number, 4-10
|
||||
*****************************************/
|
||||
void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
||||
void rs780_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u32 gfx_gpp_sb_sel;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
|
@ -371,7 +371,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
|||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEConfigureGPPCore
|
||||
*****************************************/
|
||||
void config_gpp_core(device_t nb_dev, device_t sb_dev)
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
|
@ -396,7 +396,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
|
|||
/**
|
||||
* Hide unused Gpp port
|
||||
*/
|
||||
void pcie_hide_unused_ports(device_t nb_dev)
|
||||
void pcie_hide_unused_ports(struct device *nb_dev)
|
||||
{
|
||||
u16 hide = 0x6FC; /* skip port 0, 1, 8 */
|
||||
|
||||
|
|
Loading…
Reference in New Issue