mb/purism/librem_skl: Convert to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier
Patrick Georgi
parent
fcd9f36b6e
commit
57e37c5863
|
|
@ -39,9 +39,9 @@ config MAINBOARD_DIR
|
|||
string
|
||||
default "purism/librem_skl"
|
||||
|
||||
config DEVICETREE
|
||||
config OVERRIDE_DEVICETREE
|
||||
string
|
||||
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
|
||||
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
|
|
|
|||
|
|
@ -167,19 +167,6 @@ chip soc/intel/skylake
|
|||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD
|
||||
|
||||
# OC1 should be for Type-C but it seems to not have been wired, according to
|
||||
# the available schematics, even though it is labeled as USB_OC_TYPEC.
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
|
||||
# PL2 override 25W
|
||||
register "tdp_pl2_override" = "25"
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD
|
||||
|
||||
# OC1 should be for Type-C but it seems to not have been wired, according to
|
||||
# the available schematics, even though it is labeled as USB_OC_TYPEC.
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
|
||||
device domain 0 on end
|
||||
end
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
register "gpu_pp_up_delay_ms" = "200"
|
||||
register "gpu_pp_down_delay_ms" = " 50"
|
||||
register "gpu_pp_cycle_delay_ms" = "500"
|
||||
register "gpu_pp_backlight_on_delay_ms" = " 1"
|
||||
register "gpu_pp_backlight_off_delay_ms" = "200"
|
||||
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# IGD Displays
|
||||
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
||||
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
||||
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# Set the Thermal Control Circuit (TCC) activaction value to 95C
|
||||
# even though FSP integration guide says to set it to 100C for SKL-U
|
||||
# (offset at 0), because when the TCC activates at 100C, the CPU
|
||||
# will have already shut itself down from overheating protection.
|
||||
register "tcc_offset" = "5" # TCC of 95C
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_C"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
|
||||
register "gen1_dec" = "0x00000381"
|
||||
register "gen2_dec" = "0x000c0081"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
# FSP Configuration
|
||||
register "ProbelessTrace" = "0"
|
||||
register "EnableLan" = "0"
|
||||
register "EnableSata" = "1"
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "0"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsDevSlp[0]" = "0"
|
||||
register "SataPortsDevSlp[2]" = "0"
|
||||
register "EnableAzalia" = "1"
|
||||
register "DspEnable" = "0"
|
||||
register "IoBufferOwnership" = "0"
|
||||
register "EnableTraceHub" = "0"
|
||||
register "SsicPortEnable" = "0"
|
||||
register "SmbusEnable" = "1"
|
||||
register "Cio2Enable" = "0"
|
||||
register "ScsEmmcEnabled" = "0"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "0"
|
||||
register "PttSwitch" = "0"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "Device4Enable" = "1"
|
||||
register "HeciEnabled" = "0"
|
||||
register "SaGv" = "3"
|
||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||
register "PmConfigSlpS4MinAssert" = "1" # 1s
|
||||
register "PmConfigSlpSusMinAssert" = "3" # 500ms
|
||||
register "PmConfigSlpAMinAssert" = "3" # 2s
|
||||
register "PmTimerDisabled" = "0"
|
||||
|
||||
# EC/KBC requires continuous mode
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Domain/Setting | SA | IA | GT Unsliced | GT |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 4A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| IccMax | 7A | 34A | 35A | 35A |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
|
||||
#| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(4),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(7),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1500,
|
||||
.dc_loadline = 1430,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(34),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 570,
|
||||
.dc_loadline = 483,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(35),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 520,
|
||||
.dc_loadline = 420,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(35),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 520,
|
||||
.dc_loadline = 420,
|
||||
}"
|
||||
|
||||
# Enable Root Ports 5 and 9
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
# Enable CLKREQ# for RP9
|
||||
register "PcieRpClkReqSupport[8]" = "1"
|
||||
# SRCCLKREQ2# for NVMe per schematic
|
||||
register "PcieRpClkReqNumber[8]" = "2"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
|
||||
|
||||
# OC0 should be for Type-C but it seems to not have been wired, according to
|
||||
# the available schematics, even though it is labeled as USB_OC_TYPEC.
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
|
||||
# PL2 override 25W
|
||||
register "tdp_pl2_override" = "25"
|
||||
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 on end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1f.0 on
|
||||
chip ec/purism/librem
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
# Enable CLKREQ# for RP9
|
||||
register "PcieRpClkReqSupport[8]" = "1"
|
||||
# SRCCLKREQ2# for NVMe per schematic
|
||||
register "PcieRpClkReqNumber[8]" = "2"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
|
||||
|
||||
# OC0 should be for Type-C but it seems to not have been wired, according to
|
||||
# the available schematics, even though it is labeled as USB_OC_TYPEC.
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
|
||||
|
||||
device domain 0 on
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue