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src/soc: change "unsigned" to "unsigned int" 

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Martin Roth 2019-10-23 21:45:23 -06:00 committed by Martin Roth
parent ad0f485361
commit 57e8909081
67 changed files with 295 additions and 295 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/cavium/cn81xx/twsi.c
View File

@ -667,7 +667,7 @@ int twsi_init(unsigned int bus, enum i2c_speed hz)
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int seg_count)
{
int result;

2
src/soc/imgtec/pistachio/include/soc/gpio.h
View File

@ -16,6 +16,6 @@
#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__
#define __SOC_IMGTECH_PISTACHIO_GPIO_H__
typedef unsigned gpio_t;
typedef unsigned int gpio_t;
#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__

2
src/soc/imgtec/pistachio/monotonic_timer.c
View File

@ -24,7 +24,7 @@
static int get_count_mhz_freq(void)
{
static unsigned count_mhz_freq;
static unsigned int count_mhz_freq;
if (!count_mhz_freq) {
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)

16
src/soc/imgtec/pistachio/uart.c
View File

@ -34,12 +34,12 @@
#define UART_SHIFT 2
#define GEN_ACCESSOR(name, idx) \
static inline uint8_t read_##name(unsigned base_port) \
static inline uint8_t read_##name(unsigned int base_port) \
{ \
return read8((void *)(base_port + (idx << UART_SHIFT))); \
} \
\
static inline void write_##name(unsigned base_port, uint8_t val) \
static inline void write_##name(unsigned int base_port, uint8_t val) \
{ \
write8((void *)(base_port + (idx << UART_SHIFT)), val); \
}
@ -54,12 +54,12 @@ GEN_ACCESSOR(lsr, UART8250_LSR)
GEN_ACCESSOR(dll, UART8250_DLL)
GEN_ACCESSOR(dlm, UART8250_DLM)
static int uart8250_mem_can_tx_byte(unsigned base_port)
static int uart8250_mem_can_tx_byte(unsigned int base_port)
{
return read_lsr(base_port) & UART8250_LSR_THRE;
}
static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
static void uart8250_mem_tx_byte(unsigned int base_port, unsigned char data)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i-- && !uart8250_mem_can_tx_byte(base_port))
@ -67,19 +67,19 @@ static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
write_tbr(base_port, data);
}
static void uart8250_mem_tx_flush(unsigned base_port)
static void uart8250_mem_tx_flush(unsigned int base_port)
{
unsigned long int i = FIFO_TIMEOUT;
while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT))
udelay(1);
}
static int uart8250_mem_can_rx_byte(unsigned base_port)
static int uart8250_mem_can_rx_byte(unsigned int base_port)
{
return read_lsr(base_port) & UART8250_LSR_DR;
}
static unsigned char uart8250_mem_rx_byte(unsigned base_port)
static unsigned char uart8250_mem_rx_byte(unsigned int base_port)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i-- && !uart8250_mem_can_rx_byte(base_port))
@ -90,7 +90,7 @@ static unsigned char uart8250_mem_rx_byte(unsigned base_port)
return 0x0;
}
static void uart8250_mem_init(unsigned base_port, unsigned divisor)
static void uart8250_mem_init(unsigned int base_port, unsigned int divisor)
{
/* Disable interrupts */
write_ier(base_port, 0x0);

2
src/soc/intel/baytrail/include/soc/msr.h
View File

@ -39,7 +39,7 @@
#define MSR_CPU_THERM_SENS_CFG 0x675
/* Read BCLK from MSR */
unsigned bus_freq_khz(void);
unsigned int bus_freq_khz(void);
void set_max_freq(void);
#endif /* _BAYTRAIL_MSR_H_ */

2
src/soc/intel/baytrail/include/soc/pattrs.h
View File

@ -42,7 +42,7 @@ struct pattrs {
const void *microcode_patch;
int address_bits;
int num_cpus;
unsigned bclk_khz;
unsigned int bclk_khz;
};
/* This is just to hide the abstraction w/o relying on how the underlying

2
src/soc/intel/baytrail/lpe.c
View File

@ -42,7 +42,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index)
{
struct resource *res;

2
src/soc/intel/baytrail/southcluster.c
View File

@ -351,7 +351,7 @@ static void hda_work_around(struct device *dev)
static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
unsigned int offset;
/* Parts of the HDA block are used for LPE audio as well.
* Therefore assume the HDA will never be put into D3Hot. */

18
src/soc/intel/baytrail/spi.c
View File

@ -76,7 +76,7 @@ typedef struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned databytes;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@ -140,7 +140,7 @@ static u8 readb_(const void *addr)
{
u8 v = read8((unsigned long)addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -148,7 +148,7 @@ static u16 readw_(const void *addr)
{
u16 v = read16((unsigned long)addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -156,7 +156,7 @@ static u32 readl_(const void *addr)
{
u32 v = read32((unsigned long)addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -164,21 +164,21 @@ static void writeb_(u8 b, void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@ -285,13 +285,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;

4
src/soc/intel/baytrail/tsc_freq.c
View File

@ -18,7 +18,7 @@
#include <cpu/x86/tsc.h>
#include <soc/msr.h>
unsigned bus_freq_khz(void)
unsigned int bus_freq_khz(void)
{
msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
switch (clk_info.lo & 0x3) {
@ -38,7 +38,7 @@ unsigned bus_freq_khz(void)
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
unsigned bclk_khz = bus_freq_khz();
unsigned int bclk_khz = bus_freq_khz();
if (!bclk_khz)
return 0;

2
src/soc/intel/fsp_baytrail/include/soc/msr.h
View File

@ -29,6 +29,6 @@
#define MSR_IACORE_TURBO_VIDS 0x66d
/* Read BCLK from MSR */
unsigned bus_freq_khz(void);
unsigned int bus_freq_khz(void);
#endif /* _BAYTRAIL_MSR_H_ */

2
src/soc/intel/fsp_baytrail/include/soc/pattrs.h
View File

@ -42,7 +42,7 @@ struct pattrs {
const void *microcode_patch;
int address_bits;
int num_cpus;
unsigned bclk_khz;
unsigned int bclk_khz;
};
/* This is just to hide the abstraction w/o relying on how the underlying

2
src/soc/intel/fsp_baytrail/lpe.c
View File

@ -42,7 +42,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index)
{
struct resource *res;

2
src/soc/intel/fsp_baytrail/southcluster.c
View File

@ -489,7 +489,7 @@ static void hda_work_around(struct device *dev)
static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
unsigned int offset;
/* Parts of the HDA block are used for LPE audio as well.
* Therefore assume the HDA will never be put into D3Hot. */

6
src/soc/intel/fsp_baytrail/spi.c
View File

@ -76,7 +76,7 @@ typedef struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned databytes;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
} ich_spi_controller;
@ -266,13 +266,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;

4
src/soc/intel/fsp_baytrail/tsc_freq.c
View File

@ -19,7 +19,7 @@
#include <soc/msr.h>
#include <soc/baytrail.h>
unsigned bus_freq_khz(void)
unsigned int bus_freq_khz(void)
{
msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
switch (clk_info.lo & 0x3) {
@ -39,7 +39,7 @@ unsigned bus_freq_khz(void)
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
unsigned bclk_khz = bus_freq_khz();
unsigned int bclk_khz = bus_freq_khz();
if (!bclk_khz)
return 0;

8
src/soc/intel/fsp_broadwell_de/include/soc/smbus.h
View File

@ -40,9 +40,9 @@
#define SMBUS_TIMEOUT (10 * 1000 * 100)
#define SMBUS_SLAVE_ADDR 0x24
int do_smbus_read_byte(unsigned smbus_base, unsigned device,
unsigned address);
int do_smbus_write_byte(unsigned smbus_base, unsigned device,
unsigned address, unsigned data);
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
unsigned int address);
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data);
#endif

10
src/soc/intel/fsp_broadwell_de/smbus_common.c
View File

@ -31,7 +31,7 @@ static void smbus_delay(void)
static int smbus_wait_until_ready(u16 smbus_base)
{
unsigned loops = SMBUS_TIMEOUT;
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@ -44,7 +44,7 @@ static int smbus_wait_until_ready(u16 smbus_base)
static int smbus_wait_until_done(u16 smbus_base)
{
unsigned loops = SMBUS_TIMEOUT;
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@ -55,7 +55,7 @@ static int smbus_wait_until_done(u16 smbus_base)
return loops ? 0 : -1;
}
int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
@ -101,8 +101,8 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
return byte;
}
int do_smbus_write_byte(unsigned smbus_base, unsigned device,
unsigned address, unsigned data)
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data)
{
unsigned char global_status_register;

8
src/soc/nvidia/tegra/i2c.c
View File

@ -138,7 +138,7 @@ static int tegra_i2c_send_recv(int bus, int read,
return 0;
}
static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart,
static int tegra_i2c_request(int bus, unsigned int chip, int cont, int restart,
int read, void *data, int data_len)
{
uint32_t headers[3];
@ -170,7 +170,7 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart,
data, data_len);
}
static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart,
static int i2c_transfer_segment(unsigned int bus, unsigned int chip, int restart,
int read, void *buf, int len)
{
const uint32_t max_payload =
@ -188,7 +188,7 @@ static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart,
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count)
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
{
struct i2c_msg *seg = segments;
int i;
@ -208,7 +208,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count)
return 0;
}
void i2c_init(unsigned bus)
void i2c_init(unsigned int bus)
{
struct tegra_i2c_regs *regs;

8
src/soc/nvidia/tegra/i2c.h
View File

@ -18,9 +18,9 @@
#include <stdint.h>
void i2c_init(unsigned bus);
void tegra_software_i2c_init(unsigned bus);
void tegra_software_i2c_disable(unsigned bus);
void i2c_init(unsigned int bus);
void tegra_software_i2c_init(unsigned int bus);
void tegra_software_i2c_disable(unsigned int bus);
enum {
/* Word 0 */
@ -168,6 +168,6 @@ struct tegra_i2c_regs {
};
check_member(tegra_i2c_regs, config_load, 0x8C);
extern unsigned g_num_i2c_buses;
extern unsigned int g_num_i2c_buses;
#endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */

12
src/soc/nvidia/tegra/software_i2c.c
View File

@ -36,7 +36,7 @@ static struct {
.sda = GPIO(Z7), .scl = GPIO(Z6)},
};
static void tegra_set_sda(unsigned bus, int high)
static void tegra_set_sda(unsigned int bus, int high)
{
if (high)
gpio_input_pullup(pins[bus].sda);
@ -44,7 +44,7 @@ static void tegra_set_sda(unsigned bus, int high)
gpio_output(pins[bus].sda, 0);
}
static void tegra_set_scl(unsigned bus, int high)
static void tegra_set_scl(unsigned int bus, int high)
{
if (high)
gpio_input_pullup(pins[bus].scl);
@ -52,12 +52,12 @@ static void tegra_set_scl(unsigned bus, int high)
gpio_output(pins[bus].scl, 0);
}
static int tegra_get_sda(unsigned bus)
static int tegra_get_sda(unsigned int bus)
{
return gpio_get(pins[bus].sda);
}
static int tegra_get_scl(unsigned bus)
static int tegra_get_scl(unsigned int bus)
{
return gpio_get(pins[bus].scl);
}
@ -69,7 +69,7 @@ static struct software_i2c_ops tegra_ops = {
.get_scl = tegra_get_scl,
};
void tegra_software_i2c_init(unsigned bus)
void tegra_software_i2c_init(unsigned int bus)
{
software_i2c[bus] = &tegra_ops;
@ -78,7 +78,7 @@ void tegra_software_i2c_init(unsigned bus)
tegra_set_scl(bus, 1);
}
void tegra_software_i2c_disable(unsigned bus)
void tegra_software_i2c_disable(unsigned int bus)
{
software_i2c[bus] = NULL;

2
src/soc/nvidia/tegra124/i2c.c
View File

@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = {
}
};
unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);

6
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
View File

@ -292,7 +292,7 @@ static void __noreturn reset(void)
halt();
}
static void udelay(unsigned usecs)
static void udelay(unsigned int usecs)
{
uint32_t start = read32(timer_us_ptr);
while (read32(timer_us_ptr) - start < usecs)
@ -313,7 +313,7 @@ static uint32_t get_wakeup_vector(void)
return read32(pmc_ctlr_scratch41_ptr);
}
static unsigned get_osc_freq(void)
static unsigned int get_osc_freq(void)
{
return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
@ -507,7 +507,7 @@ void ram_repair(void)
/* Power. */
static void power_on_partition(unsigned id)
static void power_on_partition(unsigned int id)
{
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {

2
src/soc/nvidia/tegra124/uart.c
View File

@ -45,7 +45,7 @@ static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr);
static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
{
// Use a hardcoded divisor for now.
const unsigned divisor = 221;
const unsigned int divisor = 221;
const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
tegra124_uart_tx_flush(uart_ptr);

2
src/soc/nvidia/tegra210/i2c.c
View File

@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = {
}
};
unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);

4
src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
View File

@ -456,7 +456,7 @@ static void __noreturn reset(void)
halt();
}
static void udelay(unsigned usecs)
static void udelay(unsigned int usecs)
{
uint32_t start = read32(timer_us_ptr);
while (read32(timer_us_ptr) - start < usecs)
@ -638,7 +638,7 @@ void ram_repair(void)
/* Power. */
static void power_on_partition(unsigned id)
static void power_on_partition(unsigned int id)
{
uint32_t bit = 0x1 << id;
if (!(read32(pmc_pwrgate_status_ptr) & bit)) {

2
src/soc/nvidia/tegra210/uart.c
View File

@ -49,7 +49,7 @@ static int tegra210_uart_tst_byte(void);
static void tegra210_uart_init(void)
{
// Use a hardcoded divisor for now.
const unsigned divisor = 221;
const unsigned int divisor = 221;
const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
tegra210_uart_tx_flush();

16
src/soc/qualcomm/ipq40xx/gpio.c
View File

@ -58,11 +58,11 @@ Return : None
*******************************************************/
void gpio_tlmm_config_set(gpio_t gpio, unsigned func,
unsigned pull, unsigned drvstr,
unsigned enable)
void gpio_tlmm_config_set(gpio_t gpio, unsigned int func,
unsigned int pull, unsigned int drvstr,
unsigned int enable)
{
unsigned val = 0;
unsigned int val = 0;
if (gpio_not_valid(gpio))
return;
@ -88,11 +88,11 @@ Return : None
*******************************************************/
void gpio_tlmm_config_get(gpio_t gpio, unsigned *func,
unsigned *pull, unsigned *drvstr,
unsigned *enable)
void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
unsigned int *pull, unsigned int *drvstr,
unsigned int *enable)
{
unsigned val;
unsigned int val;
void *addr = GPIO_CONFIG_ADDR(gpio);
if (gpio_not_valid(gpio))

2
src/soc/qualcomm/ipq40xx/i2c.c
View File

@ -152,7 +152,7 @@ static int i2c_init(blsp_qup_id_t id)
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int seg_count)
{
struct i2c_msg *seg = segments;

18
src/soc/qualcomm/ipq40xx/include/soc/cdp.h
View File

@ -33,7 +33,7 @@
#include <types.h>
unsigned smem_get_board_machtype(void);
unsigned int smem_get_board_machtype(void);
typedef enum {
PHY_INTERFACE_MODE_MII,
@ -116,17 +116,17 @@ typedef struct {
} spinorflash_params_t;
typedef struct {
unsigned count;
unsigned int count;
uint8_t addr[7];
} ipq_gmac_phy_addr_t;
typedef struct {
unsigned base;
unsigned int base;
int unit;
unsigned is_macsec;
unsigned mac_pwr0;
unsigned mac_pwr1;
unsigned mac_conn_to_phy;
unsigned int is_macsec;
unsigned int mac_pwr0;
unsigned int mac_pwr1;
unsigned int mac_conn_to_phy;
phy_interface_t phy;
ipq_gmac_phy_addr_t phy_addr;
} ipq_gmac_board_cfg_t;
@ -169,7 +169,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
}
#endif
unsigned int get_board_index(unsigned machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count);
unsigned int get_board_index(unsigned int machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count);
#endif /* _IPQ40XX_CDP_H_ */

2
src/soc/qualcomm/ipq40xx/include/soc/clock.h
View File

@ -209,7 +209,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n,
unsigned int d);
void nand_clock_config(void);
void usb_clock_config(void);
int audio_clock_config(unsigned frequency);
int audio_clock_config(unsigned int frequency);
int blsp_i2c_clock_config(blsp_qup_id_t id);

10
src/soc/qualcomm/ipq40xx/include/soc/qup.h
View File

@ -159,10 +159,10 @@ typedef enum {
typedef struct {
qup_protocol_t protocol;
unsigned clk_frequency;
unsigned src_frequency;
unsigned int clk_frequency;
unsigned int src_frequency;
qup_mode_t mode;
unsigned initialized;
unsigned int initialized;
} qup_config_t;
typedef struct {
@ -171,12 +171,12 @@ typedef struct {
struct {
uint8_t addr;
uint8_t *data;
unsigned data_len;
unsigned int data_len;
} iic;
struct {
void *in;
void *out;
unsigned size;
unsigned int size;
} spi;
} p;
} qup_data_t;

16
src/soc/qualcomm/ipq40xx/lcc.c
View File

@ -76,11 +76,11 @@ typedef struct __packed {
} IpqLccPllRegs;
struct lcc_freq_tbl {
unsigned freq;
unsigned pd;
unsigned m;
unsigned n;
unsigned d;
unsigned int freq;
unsigned int pd;
unsigned int m;
unsigned int n;
unsigned int d;
};
static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = {
@ -205,12 +205,12 @@ static int lcc_init_enable_ahbix(IpqLccClocks *bus)
return 1;
}
static int lcc_init_mi2s(IpqLccClocks *bus, unsigned freq)
static int lcc_init_mi2s(IpqLccClocks *bus, unsigned int freq)
{
IpqLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs;
uint32_t regval;
uint8_t pd, m, n, d;
unsigned i;
unsigned int i;
i = 0;
while (lcc_mi2s_freq_tbl[i].freq != 0) {
@ -285,7 +285,7 @@ static int lcc_enable_mi2s(IpqLccClocks *bus)
return 1;
}
int audio_clock_config(unsigned frequency)
int audio_clock_config(unsigned int frequency)
{
IpqLccClocks bus = {
.gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG),

12
src/soc/qualcomm/ipq40xx/qup.c
View File

@ -100,7 +100,7 @@ static int check_bit_state(uint32_t *reg, int wait_for)
/*
* Check whether GSBIn_QUP State is valid
*/
static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned wait_for)
static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for)
{
return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for);
}
@ -195,8 +195,8 @@ static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
qup_return_t ret = QUP_ERR_UNDEFINED;
uint8_t addr = p_tx_obj->p.iic.addr;
uint8_t *data_ptr = p_tx_obj->p.iic.data;
unsigned data_len = p_tx_obj->p.iic.data_len;
unsigned idx = 0;
unsigned int data_len = p_tx_obj->p.iic.data_len;
unsigned int idx = 0;
uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
qup_reset_master_status(id);
@ -312,8 +312,8 @@ static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj)
qup_return_t ret = QUP_ERR_UNDEFINED;
uint8_t addr = p_tx_obj->p.iic.addr;
uint8_t *data_ptr = p_tx_obj->p.iic.data;
unsigned data_len = p_tx_obj->p.iic.data_len;
unsigned idx = 0;
unsigned int data_len = p_tx_obj->p.iic.data_len;
unsigned int idx = 0;
uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
qup_reset_master_status(id);
@ -476,7 +476,7 @@ bailout:
qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
{
qup_return_t ret = QUP_ERR_UNDEFINED;
unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE));
unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE));
if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
/*

2
src/soc/qualcomm/ipq40xx/timer.c
View File

@ -70,7 +70,7 @@ static inline uint64_t read_gcnt_val(void)
* udelay - generates micro second delay.
* @param usec: delay duration in microseconds
*/
void udelay(unsigned usec)
void udelay(unsigned int usec)
{
uint64_t expire;

2
src/soc/qualcomm/ipq40xx/uart.c
View File

@ -44,7 +44,7 @@
typedef struct {
void *uart_dm_base;
uart_clk_mnd_t mnd_value;
unsigned blsp_uart;
unsigned int blsp_uart;
gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
} uart_params_t;

16
src/soc/qualcomm/ipq806x/gpio.c
View File

@ -59,11 +59,11 @@ Return : None
*******************************************************/
void gpio_tlmm_config_set(gpio_t gpio, unsigned func,
unsigned pull, unsigned drvstr,
unsigned enable)
void gpio_tlmm_config_set(gpio_t gpio, unsigned int func,
unsigned int pull, unsigned int drvstr,
unsigned int enable)
{
unsigned val = 0;
unsigned int val = 0;
if (gpio_not_valid(gpio))
return;
@ -89,11 +89,11 @@ Return : None
*******************************************************/
void gpio_tlmm_config_get(gpio_t gpio, unsigned *func,
unsigned *pull, unsigned *drvstr,
unsigned *enable)
void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
unsigned int *pull, unsigned int *drvstr,
unsigned int *enable)
{
unsigned val;
unsigned int val;
void *addr = GPIO_CONFIG_ADDR(gpio);
if (gpio_not_valid(gpio))

12
src/soc/qualcomm/ipq806x/gsbi.c
View File

@ -57,12 +57,12 @@ static inline void *gsbi_ctl_reg_addr(gsbi_id_t gsbi_id)
gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol)
{
unsigned reg_val;
unsigned m = 1;
unsigned n = 4;
unsigned pre_div = 4;
unsigned src = 3;
unsigned mnctr_mode = 2;
unsigned int reg_val;
unsigned int m = 1;
unsigned int n = 4;
unsigned int pre_div = 4;
unsigned int src = 3;
unsigned int mnctr_mode = 2;
void *gsbi_ctl = gsbi_ctl_reg_addr(gsbi_id);
if (!gsbi_ctl)

6
src/soc/qualcomm/ipq806x/i2c.c
View File

@ -96,9 +96,9 @@ static int i2c_write(uint32_t gsbi_id, uint8_t slave,
return 0;
}
static int i2c_init(unsigned bus)
static int i2c_init(unsigned int bus)
{
unsigned gsbi_id = bus;
unsigned int gsbi_id = bus;
qup_config_t *qup_config;
switch (gsbi_id) {
@ -139,7 +139,7 @@ static int i2c_init(unsigned bus)
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int seg_count)
{
struct i2c_msg *seg = segments;

18
src/soc/qualcomm/ipq806x/include/soc/cdp.h
View File

@ -18,7 +18,7 @@
#include <types.h>
unsigned smem_get_board_machtype(void);
unsigned int smem_get_board_machtype(void);
typedef enum {
PHY_INTERFACE_MODE_MII,
@ -101,17 +101,17 @@ typedef struct {
} spinorflash_params_t;
typedef struct {
unsigned count;
unsigned int count;
uint8_t addr[7];
} ipq_gmac_phy_addr_t;
typedef struct {
unsigned base;
unsigned int base;
int unit;
unsigned is_macsec;
unsigned mac_pwr0;
unsigned mac_pwr1;
unsigned mac_conn_to_phy;
unsigned int is_macsec;
unsigned int mac_pwr0;
unsigned int mac_pwr1;
unsigned int mac_conn_to_phy;
phy_interface_t phy;
ipq_gmac_phy_addr_t phy_addr;
} ipq_gmac_board_cfg_t;
@ -154,8 +154,8 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
}
#endif
unsigned int get_board_index(unsigned machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count);
unsigned int get_board_index(unsigned int machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count);
void board_nand_init(void);

2
src/soc/qualcomm/ipq806x/include/soc/clock.h
View File

@ -193,6 +193,6 @@ void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
unsigned int d, unsigned int clk_dummy);
void nand_clock_config(void);
void usb_clock_config(void);
int audio_clock_config(unsigned frequency);
int audio_clock_config(unsigned int frequency);
#endif /* __IPQ860X_CLOCK_H_ */

10
src/soc/qualcomm/ipq806x/include/soc/qup.h
View File

@ -145,10 +145,10 @@ typedef enum {
typedef struct {
qup_protocol_t protocol;
unsigned clk_frequency;
unsigned src_frequency;
unsigned int clk_frequency;
unsigned int src_frequency;
qup_mode_t mode;
unsigned initialized;
unsigned int initialized;
} qup_config_t;
typedef struct {
@ -157,12 +157,12 @@ typedef struct {
struct {
uint8_t addr;
uint8_t *data;
unsigned data_len;
unsigned int data_len;
} iic;
struct {
void *in;
void *out;
unsigned size;
unsigned int size;
} spi;
} p;
} qup_data_t;

16
src/soc/qualcomm/ipq806x/lcc.c
View File

@ -76,11 +76,11 @@ typedef struct __packed {
} Ipq806xLccPllRegs;
struct lcc_freq_tbl {
unsigned freq;
unsigned pd;
unsigned m;
unsigned n;
unsigned d;
unsigned int freq;
unsigned int pd;
unsigned int m;
unsigned int n;
unsigned int d;
};
static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = {
@ -205,12 +205,12 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus)
return 1;
}
static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq)
static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned int freq)
{
Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs;
uint32_t regval;
uint8_t pd, m, n, d;
unsigned i;
unsigned int i;
i = 0;
while (lcc_mi2s_freq_tbl[i].freq != 0) {
@ -285,7 +285,7 @@ static int lcc_enable_mi2s(Ipq806xLccClocks *bus)
return 1;
}
int audio_clock_config(unsigned frequency)
int audio_clock_config(unsigned int frequency)
{
Ipq806xLccClocks bus = {
.gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG),

28
src/soc/qualcomm/ipq806x/qup.c
View File

@ -37,14 +37,14 @@
#define TIMEOUT_CNT 100000
//TODO: refactor the following array to iomap driver.
static unsigned gsbi_qup_base[] = {
(unsigned)GSBI_QUP1_BASE,
(unsigned)GSBI_QUP2_BASE,
(unsigned)GSBI_QUP3_BASE,
(unsigned)GSBI_QUP4_BASE,
(unsigned)GSBI_QUP5_BASE,
(unsigned)GSBI_QUP6_BASE,
(unsigned)GSBI_QUP7_BASE,
static unsigned int gsbi_qup_base[] = {
(unsigned int)GSBI_QUP1_BASE,
(unsigned int)GSBI_QUP2_BASE,
(unsigned int)GSBI_QUP3_BASE,
(unsigned int)GSBI_QUP4_BASE,
(unsigned int)GSBI_QUP5_BASE,
(unsigned int)GSBI_QUP6_BASE,
(unsigned int)GSBI_QUP7_BASE,
};
#define QUP_ADDR(gsbi_num, reg) ((void *)((gsbi_qup_base[gsbi_num-1]) + (reg)))
@ -91,7 +91,7 @@ static int check_bit_state(uint32_t *reg, int wait_for)
/*
* Check whether GSBIn_QUP State is valid
*/
static qup_return_t qup_wait_for_state(gsbi_id_t gsbi_id, unsigned wait_for)
static qup_return_t qup_wait_for_state(gsbi_id_t gsbi_id, unsigned int wait_for)
{
return check_bit_state(QUP_ADDR(gsbi_id, QUP_STATE), wait_for);
}
@ -155,8 +155,8 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj,
qup_return_t ret = QUP_ERR_UNDEFINED;
uint8_t addr = p_tx_obj->p.iic.addr;
uint8_t *data_ptr = p_tx_obj->p.iic.data;
unsigned data_len = p_tx_obj->p.iic.data_len;
unsigned idx = 0;
unsigned int data_len = p_tx_obj->p.iic.data_len;
unsigned int idx = 0;
qup_reset_master_status(gsbi_id);
qup_set_state(gsbi_id, QUP_STATE_RUN);
@ -228,8 +228,8 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj)
qup_return_t ret = QUP_ERR_UNDEFINED;
uint8_t addr = p_tx_obj->p.iic.addr;
uint8_t *data_ptr = p_tx_obj->p.iic.data;
unsigned data_len = p_tx_obj->p.iic.data_len;
unsigned idx = 0;
unsigned int data_len = p_tx_obj->p.iic.data_len;
unsigned int idx = 0;
qup_reset_master_status(gsbi_id);
qup_set_state(gsbi_id, QUP_STATE_RUN);
@ -377,7 +377,7 @@ bailout:
qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state)
{
qup_return_t ret = QUP_ERR_UNDEFINED;
unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE));
unsigned int curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE));
if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
/*

8
src/soc/qualcomm/ipq806x/spi.c
View File

@ -632,7 +632,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
}
static int spi_xfer_tx_packet(struct ipq_spi_slave *ds,
const uint8_t *dout, unsigned out_bytes)
const uint8_t *dout, unsigned int out_bytes)
{
int ret;
@ -660,7 +660,7 @@ static int spi_xfer_tx_packet(struct ipq_spi_slave *ds,
}
static int spi_xfer_rx_packet(struct ipq_spi_slave *ds,
uint8_t *din, unsigned in_bytes)
uint8_t *din, unsigned int in_bytes)
{
int ret;
@ -711,7 +711,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
SPI_QUP_CONF_OUTPUT_ENA);
while (out_bytes) {
unsigned todo = MIN(out_bytes, MAX_PACKET_COUNT);
unsigned int todo = MIN(out_bytes, MAX_PACKET_COUNT);
ret = spi_xfer_tx_packet(ds, dout, todo);
if (ret)
@ -733,7 +733,7 @@ spi_receive:
SPI_QUP_CONF_INPUT_ENA);
while (in_bytes) {
unsigned todo = MIN(in_bytes, MAX_PACKET_COUNT);
unsigned int todo = MIN(in_bytes, MAX_PACKET_COUNT);
ret = spi_xfer_rx_packet(ds, din, todo);
if (ret)

2
src/soc/qualcomm/ipq806x/timer.c
View File

@ -72,7 +72,7 @@ void init_timer(void)
* udelay - generates micro second delay.
* @param usec: delay duration in microseconds
*/
void udelay(unsigned usec)
void udelay(unsigned int usec)
{
uint32_t now;
uint32_t last;

4
src/soc/qualcomm/ipq806x/uart.c
View File

@ -47,7 +47,7 @@
typedef struct {
void *uart_dm_base;
void *uart_gsbi_base;
unsigned uart_gsbi;
unsigned int uart_gsbi;
uart_clk_mnd_t mnd_value;
gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
} uart_params_t;
@ -194,7 +194,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
void uart_tx_byte(int idx, unsigned char data)
{
int num_of_chars = 1;
unsigned tx_data = 0;
unsigned int tx_data = 0;
void *base = uart_board_param.uart_dm_base;
/* Wait until transmit FIFO is empty. */

2
src/soc/rockchip/common/i2c.c
View File

@ -231,7 +231,7 @@ static int i2c_do_xfer(void *reg_addr, struct i2c_msg segment)
return i2c_send_stop(reg_addr) || res;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int seg_count)
{
int i;

4
src/soc/rockchip/common/include/soc/i2c.h
View File

@ -17,7 +17,7 @@
#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H
void i2c_init(unsigned int bus, unsigned int hz);
void software_i2c_attach(unsigned bus);
void software_i2c_detach(unsigned bus);
void software_i2c_attach(unsigned int bus);
void software_i2c_detach(unsigned int bus);
#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H */

2
src/soc/rockchip/rk3288/clock.c
View File

@ -669,7 +669,7 @@ int rkclk_was_watchdog_reset(void)
return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
}
unsigned rkclk_i2c_clock_for_bus(unsigned bus)
unsigned int rkclk_i2c_clock_for_bus(unsigned int bus)
{
/*i2c0,i2c2 src clk from pd_bus_pclk
other i2c src clk from peri_pclk

2
src/soc/rockchip/rk3288/include/soc/clock.h
View File

@ -56,6 +56,6 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
void rkclk_configure_edp(void);
void rkclk_configure_hdmi(void);
int rkclk_was_watchdog_reset(void);
unsigned rkclk_i2c_clock_for_bus(unsigned bus);
unsigned int rkclk_i2c_clock_for_bus(unsigned int bus);
#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */

12
src/soc/rockchip/rk3288/software_i2c.c
View File

@ -33,17 +33,17 @@ static struct {
[5]{.scl = GPIO(7, C, 4), .sda = GPIO(7, C, 3)},
};
static int get_scl(unsigned bus)
static int get_scl(unsigned int bus)
{
return gpio_get(pins[bus].scl);
}
static int get_sda(unsigned bus)
static int get_sda(unsigned int bus)
{
return gpio_get(pins[bus].sda);
}
static void set_scl(unsigned bus, int high)
static void set_scl(unsigned int bus, int high)
{
if (high)
gpio_input_pullup(pins[bus].scl);
@ -51,7 +51,7 @@ static void set_scl(unsigned bus, int high)
gpio_output(pins[bus].scl, 0);
}
static void set_sda(unsigned bus, int high)
static void set_sda(unsigned int bus, int high)
{
if (high)
gpio_input_pullup(pins[bus].sda);
@ -66,7 +66,7 @@ static struct software_i2c_ops rk_ops = {
.set_sda = set_sda,
};
void software_i2c_attach(unsigned bus)
void software_i2c_attach(unsigned int bus)
{
software_i2c[bus] = &rk_ops;
@ -101,7 +101,7 @@ void software_i2c_attach(unsigned bus)
set_sda(bus, 1);
}
void software_i2c_detach(unsigned bus)
void software_i2c_detach(unsigned int bus)
{
software_i2c[bus] = NULL;

2
src/soc/rockchip/rk3399/include/soc/clock.h
View File

@ -118,7 +118,7 @@ void rkclk_configure_tsadc(unsigned int hz);
void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
int rkclk_was_watchdog_reset(void);
uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
uint32_t rkclk_i2c_clock_for_bus(unsigned int bus);
void rkclk_configure_edp(unsigned int hz);
void rkclk_configure_mipi(void);

12
src/soc/samsung/exynos5250/clock.c
View File

@ -385,10 +385,10 @@ void set_mmc_clk(int dev_index, unsigned int div)
write32(addr, val);
}
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor)
{
unsigned shift;
unsigned mask = 0xff;
unsigned int shift;
unsigned int mask = 0xff;
u32 *reg;
/*
@ -428,10 +428,10 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
}
void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
{
unsigned shift;
unsigned mask = 0xff;
unsigned int shift;
unsigned int mask = 0xff;
u32 *reg;
switch (periph_id) {

12
src/soc/samsung/exynos5250/gpio.c
View File

@ -154,14 +154,14 @@ void gpio_set_rate(int gpio, int mode)
write32(&bank->drv, value);
}
int gpio_direction_input(unsigned gpio)
int gpio_direction_input(unsigned int gpio)
{
gpio_cfg_pin(gpio, GPIO_INPUT);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
int gpio_direction_output(unsigned int gpio, int value)
{
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value)
return 0;
}
int gpio_get_value(unsigned gpio)
int gpio_get_value(unsigned int gpio)
{
unsigned int value;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio)
return !!(value & DAT_MASK(GPIO_BIT(gpio)));
}
int gpio_set_value(unsigned gpio, int value)
int gpio_set_value(unsigned int gpio, int value)
{
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -207,7 +207,7 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 5
int gpio_read_mvl3(unsigned gpio)
int gpio_read_mvl3(unsigned int gpio)
{
int high, low;
enum mvl3 value;
@ -248,7 +248,7 @@ int gpio_read_mvl3(unsigned gpio)
*/
void gpio_info(void)
{
unsigned gpio;
unsigned int gpio;
for (gpio = 0; gpio < GPIO_MAX_PORT; gpio++) {
int cfg = gpio_get_cfg(gpio);

4
src/soc/samsung/exynos5250/i2c.c
View File

@ -233,7 +233,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len)
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int seg_count)
{
struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus];
@ -263,7 +263,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
return i2c_send_stop(regs) || res;
}
void i2c_init(unsigned bus, int speed, int slaveadd)
void i2c_init(unsigned int bus, int speed, int slaveadd)
{
struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus];

4
src/soc/samsung/exynos5250/include/soc/clk.h
View File

@ -561,7 +561,7 @@ struct st_epll_con_val {
* @param periph_id Peripheral ID of peripheral to change
* @param divisor New divisor for this peripheral's clock
*/
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor);
/**
* Low-level function to set the clock ratio for a peripheral
@ -569,7 +569,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
* @param periph_id Peripheral ID of peripheral to change
* @param divisor New divisor for this peripheral's clock
*/
void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor);
/**
* Low-level function that selects the best clock scalars for a given rate and

10
src/soc/samsung/exynos5250/include/soc/gpio.h
View File

@ -482,7 +482,7 @@ void gpio_set_rate(int gpio, int mode);
* @return -1 if the value cannot be determined. Otherwise returns
* the corresponding MVL3 enum value.
*/
int gpio_read_mvl3(unsigned gpio);
int gpio_read_mvl3(unsigned int gpio);
void gpio_info(void);
@ -510,7 +510,7 @@ void gpio_info(void);
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(unsigned gpio);
int gpio_direction_input(unsigned int gpio);
/**
* Make a GPIO an output, and set its value.
@ -519,7 +519,7 @@ int gpio_direction_input(unsigned gpio);
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(unsigned gpio, int value);
int gpio_direction_output(unsigned int gpio, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
@ -528,7 +528,7 @@ int gpio_direction_output(unsigned gpio, int value);
* @param gpio GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(unsigned gpio);
int gpio_get_value(unsigned int gpio);
/**
* Set an output GPIO's value. The GPIO must already be an output or
@ -538,7 +538,7 @@ int gpio_get_value(unsigned gpio);
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
int gpio_set_value(unsigned int gpio, int value);
/*
* Many-value logic (3 states). This can be used for inputs whereby presence

2
src/soc/samsung/exynos5250/include/soc/i2c.h
View File

@ -16,6 +16,6 @@
#ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H
#define CPU_SAMSUNG_EXYNOS5250_I2C_H
void i2c_init(unsigned bus, int speed, int slaveadd);
void i2c_init(unsigned int bus, int speed, int slaveadd);
#endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */

68
src/soc/samsung/exynos5250/include/soc/tmu.h
View File

@ -19,39 +19,39 @@
#define CPU_SAMSUNG_EXYNOS5250_TMU_H
struct tmu_reg {
unsigned triminfo;
unsigned rsvd1;
unsigned rsvd2;
unsigned rsvd3;
unsigned rsvd4;
unsigned triminfo_control;
unsigned rsvd5;
unsigned rsvd6;
unsigned tmu_control;
unsigned rsvd7;
unsigned tmu_status;
unsigned sampling_internal;
unsigned counter_value0;
unsigned counter_value1;
unsigned rsvd8;
unsigned rsvd9;
unsigned current_temp;
unsigned rsvd10;
unsigned rsvd11;
unsigned rsvd12;
unsigned threshold_temp_rise;
unsigned threshold_temp_fall;
unsigned rsvd13;
unsigned rsvd14;
unsigned past_temp3_0;
unsigned past_temp7_4;
unsigned past_temp11_8;
unsigned past_temp15_12;
unsigned inten;
unsigned intstat;
unsigned intclear;
unsigned rsvd15;
unsigned emul_con;
unsigned int triminfo;
unsigned int rsvd1;
unsigned int rsvd2;
unsigned int rsvd3;
unsigned int rsvd4;
unsigned int triminfo_control;
unsigned int rsvd5;
unsigned int rsvd6;
unsigned int tmu_control;
unsigned int rsvd7;
unsigned int tmu_status;
unsigned int sampling_internal;
unsigned int counter_value0;
unsigned int counter_value1;
unsigned int rsvd8;
unsigned int rsvd9;
unsigned int current_temp;
unsigned int rsvd10;
unsigned int rsvd11;
unsigned int rsvd12;
unsigned int threshold_temp_rise;
unsigned int threshold_temp_fall;
unsigned int rsvd13;
unsigned int rsvd14;
unsigned int past_temp3_0;
unsigned int past_temp7_4;
unsigned int past_temp11_8;
unsigned int past_temp15_12;
unsigned int inten;
unsigned int intstat;
unsigned int intclear;
unsigned int rsvd15;
unsigned int emul_con;
};
check_member(tmu_reg, emul_con, 0x80);
@ -93,7 +93,7 @@ struct tmu_data {
/* TMU device specific details and status */
struct tmu_info {
/* base Address for the TMU */
unsigned tmu_base;
unsigned int tmu_base;
/* mux Address for the TMU */
int tmu_mux;
/* pre-defined values for calibration and thresholds */

12
src/soc/samsung/exynos5420/clock.c
View File

@ -350,10 +350,10 @@ int clock_set_dwmci(enum periph_id peripheral)
return 0;
}
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor)
{
unsigned shift;
unsigned mask = 0xff;
unsigned int shift;
unsigned int mask = 0xff;
u32 *reg;
/*
@ -393,10 +393,10 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
}
void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
{
unsigned shift;
unsigned mask = 0xf;
unsigned int shift;
unsigned int mask = 0xf;
u32 *reg;
switch (periph_id) {

12
src/soc/samsung/exynos5420/gpio.c
View File

@ -154,14 +154,14 @@ void gpio_set_rate(int gpio, int mode)
write32(&bank->drv, value);
}
int gpio_direction_input(unsigned gpio)
int gpio_direction_input(unsigned int gpio)
{
gpio_cfg_pin(gpio, GPIO_INPUT);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
int gpio_direction_output(unsigned int gpio, int value)
{
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value)
return 0;
}
int gpio_get_value(unsigned gpio)
int gpio_get_value(unsigned int gpio)
{
unsigned int value;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio)
return !!(value & DAT_MASK(GPIO_BIT(gpio)));
}
int gpio_set_value(unsigned gpio, int value)
int gpio_set_value(unsigned int gpio, int value)
{
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
@ -207,7 +207,7 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 15
int gpio_read_mvl3(unsigned gpio)
int gpio_read_mvl3(unsigned int gpio)
{
int high, low;
enum mvl3 value;
@ -248,7 +248,7 @@ int gpio_read_mvl3(unsigned gpio)
*/
void gpio_info(void)
{
unsigned gpio;
unsigned int gpio;
for (gpio = 0; gpio < GPIO_MAX_PORT; gpio++) {
int cfg = gpio_get_cfg(gpio);

10
src/soc/samsung/exynos5420/i2c.c
View File

@ -82,8 +82,8 @@ struct i2c_bus
struct hsi2c_regs *hsregs;
int is_highspeed; /* High speed type, rather than I2C */
int id;
unsigned clk_cycle;
unsigned clk_div;
unsigned int clk_cycle;
unsigned int clk_div;
};
@ -255,7 +255,7 @@ enum {
static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle,
unsigned op_clk)
unsigned int op_clk)
{
struct hsi2c_regs *regs = i2c->hsregs;
unsigned long clkin = clock_get_periph_rate(i2c->periph_id);
@ -361,7 +361,7 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed)
write32(&regs->stat, I2cStatMasterXmit | I2cStatEnable);
}
void i2c_init(unsigned bus, int speed, int slaveadd)
void i2c_init(unsigned int bus, int speed, int slaveadd)
{
struct i2c_bus *i2c = &i2c_busses[bus];
@ -627,7 +627,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len)
return 0;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count)
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
{
struct i2c_bus *i2c = &i2c_busses[bus];
if (i2c->is_highspeed)

4
src/soc/samsung/exynos5420/include/soc/clk.h
View File

@ -697,7 +697,7 @@ struct st_epll_con_val {
* @param periph_id Peripheral ID of peripheral to change
* @param divisor New divisor for this peripheral's clock
*/
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor);
/**
* Low-level function to set the clock ratio for a peripheral
@ -705,7 +705,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
* @param periph_id Peripheral ID of peripheral to change
* @param divisor New divisor for this peripheral's clock
*/
void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor);
/**
* Low-level function that selects the best clock scalars for a given rate and

10
src/soc/samsung/exynos5420/include/soc/gpio.h
View File

@ -465,7 +465,7 @@ void gpio_set_rate(int gpio, int mode);
* @return -1 if the value cannot be determined. Otherwise returns
* the corresponding MVL3 enum value.
*/
int gpio_read_mvl3(unsigned gpio);
int gpio_read_mvl3(unsigned int gpio);
void gpio_info(void);
@ -493,7 +493,7 @@ void gpio_info(void);
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(unsigned gpio);
int gpio_direction_input(unsigned int gpio);
/**
* Make a GPIO an output, and set its value.
@ -502,7 +502,7 @@ int gpio_direction_input(unsigned gpio);
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(unsigned gpio, int value);
int gpio_direction_output(unsigned int gpio, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
@ -511,7 +511,7 @@ int gpio_direction_output(unsigned gpio, int value);
* @param gpio GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(unsigned gpio);
int gpio_get_value(unsigned int gpio);
/**
* Set an output GPIO's value. The GPIO must already be an output or
@ -521,7 +521,7 @@ int gpio_get_value(unsigned gpio);
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
int gpio_set_value(unsigned int gpio, int value);
/*
* Many-value logic (3 states). This can be used for inputs whereby presence

2
src/soc/samsung/exynos5420/include/soc/i2c.h
View File

@ -16,6 +16,6 @@
#ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H
#define CPU_SAMSUNG_EXYNOS5420_I2C_H
void i2c_init(unsigned bus, int speed, int slaveadd);
void i2c_init(unsigned int bus, int speed, int slaveadd);
#endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */

68
src/soc/samsung/exynos5420/include/soc/tmu.h
View File

@ -19,39 +19,39 @@
#define CPU_SAMSUNG_EXYNOS5420_TMU_H
struct tmu_reg {
unsigned triminfo;
unsigned rsvd1;
unsigned rsvd2;
unsigned rsvd3;
unsigned rsvd4;
unsigned triminfo_control;
unsigned rsvd5;
unsigned rsvd6;
unsigned tmu_control;
unsigned rsvd7;
unsigned tmu_status;
unsigned sampling_internal;
unsigned counter_value0;
unsigned counter_value1;
unsigned rsvd8;
unsigned rsvd9;
unsigned current_temp;
unsigned rsvd10;
unsigned rsvd11;
unsigned rsvd12;
unsigned threshold_temp_rise;
unsigned threshold_temp_fall;
unsigned rsvd13;
unsigned rsvd14;
unsigned past_temp3_0;
unsigned past_temp7_4;
unsigned past_temp11_8;
unsigned past_temp15_12;
unsigned inten;
unsigned intstat;
unsigned intclear;
unsigned rsvd15;
unsigned emul_con;
unsigned int triminfo;
unsigned int rsvd1;
unsigned int rsvd2;
unsigned int rsvd3;
unsigned int rsvd4;
unsigned int triminfo_control;
unsigned int rsvd5;
unsigned int rsvd6;
unsigned int tmu_control;
unsigned int rsvd7;
unsigned int tmu_status;
unsigned int sampling_internal;
unsigned int counter_value0;
unsigned int counter_value1;
unsigned int rsvd8;
unsigned int rsvd9;
unsigned int current_temp;
unsigned int rsvd10;
unsigned int rsvd11;
unsigned int rsvd12;
unsigned int threshold_temp_rise;
unsigned int threshold_temp_fall;
unsigned int rsvd13;
unsigned int rsvd14;
unsigned int past_temp3_0;
unsigned int past_temp7_4;
unsigned int past_temp11_8;
unsigned int past_temp15_12;
unsigned int inten;
unsigned int intstat;
unsigned int intclear;
unsigned int rsvd15;
unsigned int emul_con;
};
check_member(tmu_reg, emul_con, 0x80);
@ -93,7 +93,7 @@ struct tmu_data {
/* TMU device specific details and status */
struct tmu_info {
/* base Address for the TMU */
unsigned tmu_base;
unsigned int tmu_base;
/* mux Address for the TMU */
int tmu_mux;
/* pre-defined values for calibration and thresholds */