From 57fc1b91b935cf1984d87690221d6f87b9942cbf Mon Sep 17 00:00:00 2001
From: Gaggery Tsai <gaggery.tsai@intel.com>
Date: Fri, 28 Jan 2022 16:07:28 -0800
Subject: [PATCH] mb/google/brya/var/vell: Enable SaGv

This patch enables SaGv since somehow it was accidently removed
by commit a52b9c3.

BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya
      variants to baseboards")

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/google/brya/variants/vell/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index ed2ccd7765..4daf446f64 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -50,6 +50,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)"  # USB2_C3
+	register "SaGv" = "SaGv_Enabled"
 
 	# I2C Port Config
 	register "SerialIoI2cMode" = "{