updates from YhLu, plus fixes for PPC/K8 issues.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
b265254e1c
commit
57ffeb0578
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@ -7,7 +7,7 @@ end
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makerule floppy
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depends "all"
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action "mcopy -o romimage a:"
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action "mcopy -o linuxbios.rom a:"
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end
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makerule nrv2b
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@ -2,7 +2,7 @@
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#include <arch/pirq_routing.h>
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#include <string.h>
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#ifdef DEBUG
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#if DEBUG==1
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void check_pirq_routing_table(void)
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{
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const uint8_t *addr;
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@ -1,7 +1,7 @@
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#ifndef __ASM_MPSPEC_H
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#define __ASM_MPSPEC_H
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#ifdef HAVE_MP_TABLE
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#if HAVE_MP_TABLE==1
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/*
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* Structure definitions for SMP machines following the
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@ -1,6 +1,6 @@
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#include <arch/asm.h>
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#include <arch/intel.h>
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#ifdef CONFIG_SMP
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#if CONFIG_SMP==1
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#include <cpu/p6/apic.h>
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#endif
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.section ".text"
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@ -39,7 +39,7 @@ _start:
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/* set new stack */
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movl $_estack, %esp
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#ifdef CONFIG_SMP
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#if CONFIG_SMP==1
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/* Get the cpu id */
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movl $APIC_DEFAULT_BASE, %edi
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movl APIC_ID(%edi), %eax
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@ -35,7 +35,7 @@ static void cache_on(struct mem_range *mem)
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* so absolute minimum needed to get it going.
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*/
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/* OK, linux it turns out does nothing. We have to do it ... */
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#if defined(i686)
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#if i686==1
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// totalram here is in linux sizing, i.e. units of KB.
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// set_mtrr is responsible for getting it into the right units!
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setup_mtrrs(mem);
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@ -101,7 +101,7 @@ static void interrupts_on()
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apic_read(APIC_ID));
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#else /* APIC */
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#ifdef i686
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#if i686==1
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/* Only Pentium Pro and later have those MSR stuff */
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msr_t msr;
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@ -7,7 +7,7 @@ makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
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makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
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makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
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makedefine ROMCCPPFLAGS := -D__ROMCC__=0 -D__ROMCC_MINOR__=23
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makedefine ROMCCPPFLAGS := -D__ROMCC__=0 -D__ROMCC_MINOR__=34
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makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall
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makedefine HOSTCFLAGS:= -Os -Wall
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@ -116,7 +116,7 @@ end
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makerule ./romcc
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depends "$(TOP)/util/romcc/romcc.c"
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action "$(HOSTCC) -g $(HOSTCFLAGS) -DVERSION='\"0.21\"' -DRELEASE_DATE='\"7 april 2003\"' $< -o $@"
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action "$(HOSTCC) -g $(HOSTCFLAGS) -DVERSION='\"0.34\"' -DRELEASE_DATE='\"4 July 2003\"' $< -o $@"
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end
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makerule build_opt_tbl
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@ -121,6 +121,11 @@ define LINUXBIOS_VERSION
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export always
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comment "LinuxBIOS version"
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end
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define LINUXBIOS_EXTRA_VERSION
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default ""
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export used
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comment "LinuxBIOS extra version"
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end
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define LINUXBIOS_BUILD
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default "$(shell date)"
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export always
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@ -249,7 +254,7 @@ define HEAP_SIZE
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comment "Default heap size"
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end
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define _RAMBASE
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default 0x4000
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default none
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format "0x%x"
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export always
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comment "Base address of LinuxBIOS in RAM"
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@ -406,6 +411,11 @@ define CONFIG_SMP
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export always
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comment "Define if we support SMP"
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end
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define CONFIG_MAX_CPUS
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default 1
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export always
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comment "Config CPU count for this machine"
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end
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define MAX_CPUS
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default 1
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export always
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@ -57,7 +57,7 @@ void console_tx_byte(unsigned char byte)
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*/
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void post_code(uint8_t value)
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{
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#ifdef CONFIG_SERIAL_POST
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#if CONFIG_SERIAL_POST==1
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printk_info("POST: 0x%02x\n", value);
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#elsif !define(NO_POST)
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outb(value, 0x80);
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@ -1,13 +1,13 @@
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#include <console/console.h>
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#include <cpu/p5/cpuid.h>
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#ifdef i586
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#if i586==1
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#include <cpu/p6/msr.h>
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#endif
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int mtrr_check(void)
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{
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#ifdef i686
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#if i686==1
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/* Only Pentium Pro and later have MTRR */
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msr_t msr;
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printk_debug("\nMTRR check\n");
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@ -16,9 +16,11 @@ uses ARCH
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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config chip.h
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register "fixup_scsi" = "1"
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#config chip.h
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#register "fixup_scsi" = "1"
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driver mainboard.o
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driver lsi_scsi.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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@ -128,8 +130,9 @@ makerule ./auto.E
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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depends "./romcc ./auto.E"
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action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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@ -152,10 +155,10 @@ end
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southbridge amd/amd8131
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1" = "{1}"
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register "lpt" = "{1}"
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end
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#superio NSC/pc87360
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# register "com1" = "{1}"
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# register "lpt" = "{1}"
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#end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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@ -183,21 +183,21 @@ static void main(void)
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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dump_pci_device(PCI_DEV(0, 0x18, 1));
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#endif
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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msr = rdmsr(TOP_MEM2);
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print_debug("TOP_MEM2: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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/*
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#if 1
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ram_check(0x00000000, msr.lo);
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#if 0
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ram_check(0x00000000, msr.lo+(msr.hi<<32));
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#else
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#if TOTAL_CPUS < 2
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// Check 16MB of memory @ 0
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@ -1,10 +1,10 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/chip.h>
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//#include <device/chip.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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//#include "chip.h"
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//#include <part/mainboard.h>
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//#include "lsi_scsi.c"
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unsigned long initial_apicid[MAX_CPUS] =
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@ -105,7 +105,7 @@ static void onboard_scsi_fixup(void)
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*/
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}
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/*
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static void
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enable(struct chip *chip, enum chip_pass pass)
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{
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@ -135,4 +135,4 @@ struct chip_control mainboard_tyan_s2880_control = {
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enable: enable,
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name: "Tyan s2880 mainboard "
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};
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*/
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@ -919,6 +919,12 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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* [31: 8] Reserved
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*/
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PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
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//BY LYH add IOMMU 64M APERTURE
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PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70,
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PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002,
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PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300,
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//BY LYH END
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};
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int i;
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int max;
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@ -1116,7 +1122,23 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
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set_dimm_size(ctrl, sz, i);
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}
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}
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static void fill_last(unsigned long node_id,unsigned long base)
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{
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//BY LYH //Fill next base reg with right value
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unsigned i;
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unsigned base_reg;
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base &=0xffff0000;
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device_t device;
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for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
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+= PCI_DEV(0, 1, 0)) {
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for(i=node_id+1;i<=7;i++) {
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base_reg=0x40+(i<<3);
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pci_write_config32(device,base_reg,base);
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}
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}
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//BY LYH END
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}
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static void route_dram_accesses(const struct mem_controller *ctrl,
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unsigned long base_k, unsigned long limit_k)
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{
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@ -1126,6 +1148,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
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unsigned base;
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unsigned index;
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unsigned limit_reg, base_reg;
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device_t device;
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node_id = ctrl->node_id;
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index = (node_id << 3);
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@ -1143,6 +1166,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
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pci_write_config32(device, limit_reg, limit);
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pci_write_config32(device, base_reg, base);
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}
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}
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static void set_top_mem(unsigned tom_k)
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@ -1251,9 +1275,9 @@ static void order_dimms(const struct mem_controller *ctrl)
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/* Recompute the cs base register value */
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#if 1 // BY LYH Need to count from 0 for every memory controller
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csbase = ((tom - (base_k>>15))<< 21) | 1;
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print_debug("csbase=");
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print_debug_hex32(csbase);
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print_debug("\r\n");
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// print_debug("csbase=");
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// print_debug_hex32(csbase);
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// print_debug("\r\n");
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#else //BY LYH END
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csbase = (tom << 21) | 1;
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#endif
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@ -1283,12 +1307,16 @@ static void order_dimms(const struct mem_controller *ctrl)
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print_debug("\r\n");
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#endif
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route_dram_accesses(ctrl, base_k, tom_k);
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//BY LYH
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fill_last(ctrl->node_id, tom_k<<2);
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//BY LYH END
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#if 0 //BY LYH
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if(ctrl->node_id==1) {
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pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
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}
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dump_pci_device(PCI_DEV(0, 0x18, 1));
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// if(ctrl->node_id==1) {
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// pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
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// }
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#endif
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set_top_mem(tom_k);
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