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soc/skl: set IGD resources only if device is enabled 

If the Intel IGD device pci 02.0 is disabled or undefined in
the device tree, then internal graphics pre-allocated memory
and GFX-VT MMIO memory for virtualization won`t be allocated
in the SoC address space.

Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby
Lake processors when the IGD device is disabled. This should
provide to run FSP 2.0-based coreboot on these CPUs families
without integrated graphics card.

The following boards were used for testing:

- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060
  as external GPU.

  Virtualization and GFX 3D acceleration with nouveau driver
  still works well  (tested on VirtualBox 5.1.38 with Ubuntu
  18.04.1 as guest and host OS)

- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.

Payload: tianocore edk2-stable201811-216-g51be9d0.

Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2019-04-25 12:32:15 +03:00 committed by Patrick Georgi
parent 5a69491a01
commit 5806665059
4 changed files with 38 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/skylake/include/soc/systemagent.h
View File

@ -48,9 +48,17 @@
bool soc_is_vtd_capable(void);
static const struct sa_mmio_descriptor soc_vtd_resources[] = {
{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = {
GFXVTBAR,
GFXVT_BASE_ADDRESS,
GFXVT_BASE_SIZE,
"GFXVTBAR"
};
static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = {
VTVC0BAR,
VTVC0_BASE_ADDRESS,
VTVC0_BASE_SIZE,
"VTVC0BAR"
};
#endif

18
src/soc/intel/skylake/romstage/romstage_fsp20.c
View File

@ -264,14 +264,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
int i;
uint32_t mask = 0;
/*
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not
* have access to the bios_reserved range so it always assumes 8MB is
* used and so the kernel will avoid the last 8MB of the stolen window.
* With the default stolen size of 32MB(-8MB) there is not enough space
* for FBC to work with a high resolution panel.
*/
m_cfg->IgdDvmt50PreAlloc = 2;
m_cfg->MmioSize = 0x800; /* 2GB in MB */
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
@ -311,12 +303,22 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
* the FSP does not initialize this device
*/
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
if (config->PrimaryDisplay == Display_iGFX)
m_cfg->PrimaryDisplay = Display_Auto;
else
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
} else {
m_cfg->InternalGfx = 1;
/*
* Set IGD stolen size to 64MB. The FBC hardware for skylake
* does not have access to the bios_reserved range so it always
* assumes 8MB is used and so the kernel will avoid the last
* 8MB of the stolen window. With the default stolen size of
* 32MB(-8MB) there is not enough space for FBC to work with
* a high resolution panel
*/
m_cfg->IgdDvmt50PreAlloc = 2;
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
}
}

12
src/soc/intel/skylake/romstage/systemagent.c
View File

@ -26,11 +26,12 @@
static void systemagent_vtd_init(void)
{
const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD);
const struct soc_intel_skylake_config *config = NULL;
if (dev)
config = dev->chip_info;
if (root_dev)
config = root_dev->chip_info;
if (config && config->ignore_vtd)
return;
@ -39,7 +40,10 @@ static void systemagent_vtd_init(void)
if (!vtd_capable)
return;
sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources));
if (igd_dev && igd_dev->enabled)
sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1);
sa_set_mch_bar(&soc_vtvc0_mmio_descriptor, 1);
}
void systemagent_early_init(void)

12
src/soc/intel/skylake/systemagent.c
View File

@ -42,6 +42,7 @@ bool soc_is_vtd_capable(void)
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
struct device *const igd_dev = SA_DEV_IGD;
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
"PCIEXBAR" },
@ -56,9 +57,14 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
ARRAY_SIZE(soc_fixed_resources));
if (!(config && config->ignore_vtd) && soc_is_vtd_capable())
sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
ARRAY_SIZE(soc_vtd_resources));
if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) {
if (igd_dev && igd_dev->enabled)
sa_add_fixed_mmio_resources(dev, index,
&soc_gfxvt_mmio_descriptor, 1);
sa_add_fixed_mmio_resources(dev, index,
&soc_vtvc0_mmio_descriptor, 1);
}
}
/*