From 58133c29fee609d4810bde125a2f18b4d91b72b1 Mon Sep 17 00:00:00 2001 From: "David W. Hendricks" Date: Wed, 26 May 2004 17:21:02 +0000 Subject: [PATCH] Early work on IWill DK8S2 motherboard. Tweaking in progress. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/Iwill/DK8S2/Config.lb | 63 +++++++++++++++------ src/mainboard/Iwill/DK8S2/auto.c | 54 ++++++++++++++---- src/mainboard/Iwill/DK8S2/chip.h | 4 +- src/mainboard/Iwill/DK8S2/cmos.layout | 4 ++ src/mainboard/Iwill/DK8S2/failover.c | 2 +- src/mainboard/Iwill/DK8S2/irq_tables.c | 77 +++++++++++--------------- src/mainboard/Iwill/DK8S2/mainboard.c | 4 +- 7 files changed, 129 insertions(+), 79 deletions(-) diff --git a/src/mainboard/Iwill/DK8S2/Config.lb b/src/mainboard/Iwill/DK8S2/Config.lb index 626eb73d2e..e11c87901c 100644 --- a/src/mainboard/Iwill/DK8S2/Config.lb +++ b/src/mainboard/Iwill/DK8S2/Config.lb @@ -171,8 +171,8 @@ makerule ./failover.inc end makerule ./auto.E - depends "$(MAINBOARD)/auto.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" + depends "$(MAINBOARD)/auto.c option_table.h" + action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end makerule ./auto.inc depends "./auto.E ./romcc" @@ -264,21 +264,50 @@ northbridge amd/amdk8 "mc0" pci 1:0.1 on pci 1:0.2 on pci 1:1.0 off - superio winbond/w83627thf link 1 - pnp 2e.0 - pnp 2e.1 - pnp 2e.2 - pnp 2e.3 - pnp 2e.4 - pnp 2e.5 - pnp 2e.6 - pnp 2e.7 - pnp 2e.8 - pnp 2e.9 - pnp 2e.a - register "com1" = "{1, 0, 0x3f8, 4}" - register "lpt" = "{1}" - end + + superio winbond/w83627hf link 1 + pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + # pnp 2e.1 off # Parallel Port + # io 0x60 = 0x378 + # irq 0x70 = 7 + pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + pnp 2e.6 off # CIR + pnp 2e.7 off # GAME_MIDI_GIPO1 + pnp 2e.8 off # GPIO2 + pnp 2e.9 off # GPIO3 + pnp 2e.a off # ACPI + pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + +# superio winbond/w83627hf link 1 +# pnp 2e.0 +# pnp 2e.1 +# pnp 2e.2 +# pnp 2e.3 +# pnp 2e.4 +# pnp 2e.5 +# pnp 2e.6 +# pnp 2e.7 +# pnp 2e.8 +# pnp 2e.9 +# pnp 2e.a +# register "com1" = "{1, 0, 0x3f8, 4}" +# register "lpt" = "{1}" +# end end end diff --git a/src/mainboard/Iwill/DK8S2/auto.c b/src/mainboard/Iwill/DK8S2/auto.c index 6626878668..9bc42ae64e 100644 --- a/src/mainboard/Iwill/DK8S2/auto.c +++ b/src/mainboard/Iwill/DK8S2/auto.c @@ -1,14 +1,17 @@ #define ASSEMBLY 1 #include #include -#include #include -#include +#include +#include #include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/early_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/k8/apic_timer.c" @@ -17,8 +20,26 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#define SIO_BASE 0x2e +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void hard_reset(void) +{ + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); + } + + static void soft_reset(void) + { + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); + } + static void memreset_setup(void) { @@ -102,6 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" +#if 0 static void enable_lapic(void) { @@ -154,6 +176,7 @@ static void pc87360_enable_serial(void) pnp_set_enable(SIO_BASE, 1); pnp_set_iobase0(SIO_BASE, 0x3f8); } +#endif #define FIRST_CPU 1 #define SECOND_CPU 1 @@ -188,22 +211,31 @@ static void main(void) }, #endif }; + int needs_reset; + + enable_lapic(); + init_timer(); + if (cpu_init_detected()) { asm("jmp __cpu_reset"); } - enable_lapic(); - init_timer(); + + distinguish_cpu_resets(); if (!boot_cpu()) { stop_this_cpu(); } - pc87360_enable_serial(); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - + needs_reset = setup_coherent_ht_domain(); + needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + #if 0 print_pci_devices(); #endif diff --git a/src/mainboard/Iwill/DK8S2/chip.h b/src/mainboard/Iwill/DK8S2/chip.h index ba52d6dbdb..6c0dd885a0 100644 --- a/src/mainboard/Iwill/DK8S2/chip.h +++ b/src/mainboard/Iwill/DK8S2/chip.h @@ -1,5 +1,5 @@ -extern struct chip_control mainboard_arima_hdama_control; +extern struct chip_control mainboard_Iwill_DK8S2_control; -struct mainboard_arima_hdama_config { +struct mainboard_Iwill_DK8S2_config { int nothing; }; diff --git a/src/mainboard/Iwill/DK8S2/cmos.layout b/src/mainboard/Iwill/DK8S2/cmos.layout index 5ba4c032c1..4a92876b07 100644 --- a/src/mainboard/Iwill/DK8S2/cmos.layout +++ b/src/mainboard/Iwill/DK8S2/cmos.layout @@ -29,6 +29,9 @@ entries 386 1 e 1 ECC_memory 388 4 r 0 reboot_bits 392 3 e 5 baud_rate +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock + 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first @@ -36,6 +39,7 @@ entries 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown +444 1 e 1 nmi 1008 16 h 0 check_sum enumerations diff --git a/src/mainboard/Iwill/DK8S2/failover.c b/src/mainboard/Iwill/DK8S2/failover.c index bd9c17020e..e40891b50d 100644 --- a/src/mainboard/Iwill/DK8S2/failover.c +++ b/src/mainboard/Iwill/DK8S2/failover.c @@ -14,7 +14,7 @@ static void main(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(0); + enumerate_ht_chain(); /* Setup the 8111 */ amd8111_enable_rom(); diff --git a/src/mainboard/Iwill/DK8S2/irq_tables.c b/src/mainboard/Iwill/DK8S2/irq_tables.c index 9be2d1cf14..a2b973f245 100644 --- a/src/mainboard/Iwill/DK8S2/irq_tables.c +++ b/src/mainboard/Iwill/DK8S2/irq_tables.c @@ -1,52 +1,37 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + #include -#include - -#define IRQ_ROUTER_BUS 1 -#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) -#define IRQ_ROUTER_VENDOR 0x1022 -#define IRQ_ROUTER_DEVICE 0x746b - -#define AVAILABLE_IRQS 0xdef8 -#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ - { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \ - {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} - -/* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu - */ const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT - * devices on the bus */ - IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ - IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ - 0x00, /* IRQs devoted exclusively to PCI usage */ - IRQ_ROUTER_VENDOR, /* Vendor */ - IRQ_ROUTER_DEVICE, /* Device */ - 0x00, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x00, /* u8 checksum , mod 256 checksum must give - * zero, will be corrected later - */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*12, /* there can be total 12 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - - /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ - - /* PCI Slot 1-6 */ - IRQ_SLOT (1, 3,1,0, 2,3,4,1 ), - IRQ_SLOT (2, 3,2,0, 3,4,1,2 ), - IRQ_SLOT (3, 2,1,0, 2,3,4,1 ), - IRQ_SLOT (4, 2,2,0, 3,4,1,2 ), - IRQ_SLOT (5, 4,5,0, 2,3,4,1 ), - IRQ_SLOT (6, 4,4,0, 1,2,3,4 ), - - /* Onboard NICs */ - IRQ_SLOT (0, 2,3,0, 4,0,0,0 ), - IRQ_SLOT (0, 2,4,0, 4,0,0,0 ), - - /* Let Linux know about bus 1 */ - IRQ_SLOT (0, 1,4,3, 0,0,0,0 ), + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0}, + {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0}, + {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0}, + {0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0}, + {0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0}, + {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0}, + {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0}, + {0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/Iwill/DK8S2/mainboard.c b/src/mainboard/Iwill/DK8S2/mainboard.c index 82041282f6..48ea1ac88b 100644 --- a/src/mainboard/Iwill/DK8S2/mainboard.c +++ b/src/mainboard/Iwill/DK8S2/mainboard.c @@ -34,8 +34,8 @@ static void enumerate(struct chip *chip) child->bus = &dev_root.link[0]; } } -struct chip_control mainboard_arima_hdama_control = { +struct chip_control mainboard_Iwill_DK8S2_control = { .enumerate = enumerate, - .name = "Arima HDAMA mainboard ", + .name = "Iwill DK8S2 mainboard ", };