diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index 8fcbb5260f..f3436c0031 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -173,7 +173,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
 void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	struct device *lpcdev = dev_find_slot(FADT_SOC_LPC_DEV);
+	struct device *lpcdev = dev_find_slot(0, FADT_SOC_LPC_DEVFN);
 	u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
 	config_t *config = lpcdev->chip_info;
 
diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h
index 832fb31e22..5abe719e44 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h
@@ -17,7 +17,7 @@
 #ifndef _BAYTRAIL_LPC_H_
 #define _BAYTRAIL_LPC_H_
 
-#define FADT_SOC_LPC_DEV 0, PCI_DEVFN(0x1f,0)
+#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
 
 /* PCI config registers in LPC bridge. */
 #define REVID		0x08
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index efe5412c9f..fbdc6e320b 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -34,7 +34,7 @@ typedef struct southbridge_intel_fsp_rangeley_config config_t;
 void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	struct device *lpcdev = dev_find_slot(SOC_LPC_DEVFN);
+	struct device *lpcdev = dev_find_slot(0, SOC_LPC_DEVFN);
 	u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
 	config_t *config = lpcdev->chip_info;
 
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index ffadee4bf2..02e410d8e7 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -92,7 +92,7 @@ void rangeley_sb_early_initialization(void);
 
 /* PCI Configuration Space (D31:F0): LPC */
 #define SOC_LPC_DEV		PCI_DEV(0, 0x1f, 0)
-#define SOC_LPC_DEVFN 0, PCI_DEVFN(0x1f,0)
+#define SOC_LPC_DEVFN		PCI_DEVFN(0x1f, 0)
 
 
 /* Southbridge IO BARs */