riscv: add the lowrisc System On Chip support
Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17119 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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config SOC_LOWRISC_LOWRISC
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select ARCH_RISCV
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select ARCH_BOOTBLOCK_RISCV
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select ARCH_VERSTAGE_RISCV
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select ARCH_ROMSTAGE_RISCV
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select ARCH_RAMSTAGE_RISCV
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART_8250MEM_32
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bool
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default n
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if SOC_LOWRISC_LOWRISC
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endif
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ifeq ($(CONFIG_SOC_LOWRISC_LOWRISC),y)
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romstage-y += cbmem.c
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ramstage-y += cbmem.c
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endif
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cbmem.h>
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void *cbmem_top(void)
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{
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// TODO: find out how the lowrisc SOC decides to provide
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// this information, when they know.
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printk(BIOS_SPEW, "Returning hard-coded 128M; fix me\n");
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return (void *)((uintptr_t)(2ULL*GiB+128*MiB));
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}
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