riscv: add the lowrisc System On Chip support

Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17119
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

src/soc/lowrisc/lowrisc/Kconfig

@@ -0,0 +1,14 @@
+config SOC_LOWRISC_LOWRISC
+	select ARCH_RISCV
+	select ARCH_BOOTBLOCK_RISCV
+	select ARCH_VERSTAGE_RISCV
+	select ARCH_ROMSTAGE_RISCV
+	select ARCH_RAMSTAGE_RISCV
+	select BOOTBLOCK_CONSOLE
+	select DRIVERS_UART_8250MEM_32
+	bool
+	default n
+
+if SOC_LOWRISC_LOWRISC
+
+endif

src/soc/lowrisc/lowrisc/Makefile.inc

@@ -0,0 +1,6 @@
+ifeq ($(CONFIG_SOC_LOWRISC_LOWRISC),y)
+
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+
+endif

src/soc/lowrisc/lowrisc/cbmem.c

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	// TODO: find out how the lowrisc SOC decides to provide
+	// this information, when they know.
+	printk(BIOS_SPEW, "Returning hard-coded 128M; fix me\n");
+	return (void *)((uintptr_t)(2ULL*GiB+128*MiB));
+}