google/kahlee: Enable TPM

Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.

Note, Kahlee TPM is on SPI, but decoded by the LPC block.

BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.

Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/kahlee/Kconfig

@@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select GFXUMA
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select SERIRQ_CONTINUOUS_MODE
 	select STONEYRIDGE_UART
 
@@ -51,7 +52,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	default y
 
 config VBOOT
-	select VBOOT_MOCK_SECDATA
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH
 	select VBOOT_VBNV_CMOS

src/mainboard/google/kahlee/bootblock/bootblock.c

@@ -15,9 +15,13 @@
 
 #include <bootblock_common.h>
 #include <ec.h>
+#include <soc/hudson.h>
 
 void bootblock_mainboard_init(void)
 {
 	/* Enable the EC as soon as we have visibility */
 	mainboard_ec_init();
+
+	/* Setup TPM decode before verstage */
+	hudson_tpm_decode_spi();
 }

src/mainboard/google/kahlee/devicetree.cb

@@ -48,6 +48,9 @@ chip soc/amd/stoneyridge
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 		end # LPC	0x790e
 		device pci 14.7 on  end # SD
 		device pci 18.0 on  end