GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drivers/intel/fsp*: Use newly added post codes for memory param prep 

This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.

Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.

Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-10-16 11:54:37 -07:00 committed by Patrick Georgi
parent 9706359fd8
commit 585210ad58
3 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/drivers/intel/fsp1_1/raminit.c
View File

@ -64,7 +64,7 @@ void raminit(struct romstage_params *params)
* set to NULL. This indicates that the FSP code will use the UPD
* region in the FSP binary.
*/
post_code(0x34);
post_code(POST_MEM_PREINIT_PREP_START);
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
@ -103,7 +103,7 @@ void raminit(struct romstage_params *params)
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&memory_init_params);
post_code(0x36);
post_code(POST_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))

2
src/drivers/intel/fsp1_1/romstage.c
View File

@ -344,7 +344,7 @@ __weak int mrc_cache_stash_data(int type, uint32_t version,
/* Transition RAM from off or self-refresh to active */
__weak void raminit(struct romstage_params *params)
{
post_code(0x34);
post_code(POST_MEM_PREINIT_PREP_START);
die("ERROR - No RAM initialization specified!\n");
}

4
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -273,7 +273,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
FSPM_ARCH_UPD *arch_upd;
uint32_t fsp_version;
post_code(0x34);
post_code(POST_MEM_PREINIT_PREP_START);
fsp_version = fsp_memory_settings_version(hdr);
@ -301,6 +301,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&fspm_upd.FspmConfig);
post_code(POST_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);