northbridge/amd/amdht: Allow mainboards to set HT frequency limit
This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -1,6 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -1002,6 +1003,10 @@ struct nodes_info_t {
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u32 up_planes; // down planes will be [up_planes, planes)
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} __attribute__((packed));
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struct ht_link_config {
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uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default)
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};
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/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/
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struct sys_info {
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@ -1015,6 +1020,8 @@ struct sys_info {
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u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it
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u16 host_link_freq_cap[NODE_NUMS*8]; //cap
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struct ht_link_config ht_link_cfg;
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u32 segbit;
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u32 sbdn;
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u32 sblk;
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@ -75,6 +75,41 @@ static const uint16_t ht_speed_limit[16] =
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0x00FF, 0x007F, 0x003F, 0x001F,
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0x000F, 0x0007, 0x0003, 0x0001};
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static const struct ht_speed_limit_map_t {
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uint16_t mhz;
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uint8_t config;
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} ht_speed_limit_map[] = {
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{0, NVRAM_LIMIT_HT_SPEED_AUTO},
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{200, NVRAM_LIMIT_HT_SPEED_200},
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{300, NVRAM_LIMIT_HT_SPEED_300},
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{400, NVRAM_LIMIT_HT_SPEED_400},
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{500, NVRAM_LIMIT_HT_SPEED_500},
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{600, NVRAM_LIMIT_HT_SPEED_600},
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{800, NVRAM_LIMIT_HT_SPEED_800},
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{1000, NVRAM_LIMIT_HT_SPEED_1000},
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{1200, NVRAM_LIMIT_HT_SPEED_1200},
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{1400, NVRAM_LIMIT_HT_SPEED_1400},
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{1600, NVRAM_LIMIT_HT_SPEED_1600},
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{1800, NVRAM_LIMIT_HT_SPEED_1800},
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{2000, NVRAM_LIMIT_HT_SPEED_2000},
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{2200, NVRAM_LIMIT_HT_SPEED_2200},
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{2400, NVRAM_LIMIT_HT_SPEED_2400},
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{2600, NVRAM_LIMIT_HT_SPEED_2600},
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};
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static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++)
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if (ht_speed_limit_map[i].mhz == mhz)
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return ht_speed_limit_map[i].config;
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printk(BIOS_WARNING,
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"WARNING: Invalid HT link limit frequency %d specified, ignoring...\n",
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mhz);
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return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO];
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}
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/*----------------------------------------------------------------------------
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* TYPEDEFS AND STRUCTURES
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*
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@ -1359,10 +1394,9 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
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for (i = 0; i < pDat->TotalLinks*2; i += 2)
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{
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/* FIXME
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* Mainboards need to be able to set cbPCBFreqLimit
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*/
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cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration
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if (pDat->HtBlock->ht_link_configuration)
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cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit);
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cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM);
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#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8
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@ -1,6 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -462,6 +463,8 @@ typedef struct {
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const u8 *pEventData0
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);
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const struct ht_link_config *ht_link_configuration;
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} AMD_HTBLOCK;
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/*
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@ -139,7 +139,8 @@ static void amd_ht_init(struct sys_info *sysinfo)
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NULL, // BOOL (*AMD_CB_CustomizeBuffers)();
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NULL, // void (*AMD_CB_OverrideDevicePort)();
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NULL, // void (*AMD_CB_OverrideCpuPort)();
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AMD_CB_EventNotify // void (*AMD_CB_EventNotify) ();
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AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) ();
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&sysinfo->ht_link_cfg // struct ht_link_config*
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};
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printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
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