Drop Intel E7520 and E7525 and related boards
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Stefan Reinauer
parent
61ed48c923
commit
5878bbd935
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@ -17,8 +17,6 @@ config BOARD_INTEL_EAGLEHEIGHTS
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bool "EagleHeights"
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config BOARD_INTEL_EMERALDLAKE2
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bool "Emerald Lake 2 CRB"
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config BOARD_INTEL_JARRELL
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bool "Jarrell (SE7520JR2)"
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config BOARD_INTEL_MINNOWMAX
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bool "Minnow Max"
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config BOARD_INTEL_MOHONPEAK
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@ -27,8 +25,6 @@ config BOARD_INTEL_MTARVON
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bool "3100 devkit (Mt. Arvon)"
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config BOARD_INTEL_TRUXTON
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bool "EP80579 devkit (Truxton)"
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config BOARD_INTEL_XE7501DEVKIT
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bool "XE7501devkit"
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config BOARD_INTEL_BASKING_RIDGE
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bool "Basking Ridge CRB"
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config BOARD_INTEL_WTM2
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@ -44,12 +40,10 @@ source "src/mainboard/intel/d945gclf/Kconfig"
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source "src/mainboard/intel/eagleheights/Kconfig"
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source "src/mainboard/intel/emeraldlake2/Kconfig"
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source "src/mainboard/intel/baskingridge/Kconfig"
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source "src/mainboard/intel/jarrell/Kconfig"
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source "src/mainboard/intel/minnowmax/Kconfig"
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source "src/mainboard/intel/mohonpeak/Kconfig"
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source "src/mainboard/intel/mtarvon/Kconfig"
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source "src/mainboard/intel/truxton/Kconfig"
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source "src/mainboard/intel/xe7501devkit/Kconfig"
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source "src/mainboard/intel/wtm2/Kconfig"
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config MAINBOARD_VENDOR
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@ -1,39 +0,0 @@
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if BOARD_INTEL_JARRELL
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7520
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select SOUTHBRIDGE_INTEL_PXHD
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select SOUTHBRIDGE_INTEL_I82801EX
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select SUPERIO_NSC_PC87427
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select ROMCC
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select UDELAY_TSC
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select USE_WATCHDOG_ON_BOOT
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select DRIVERS_ATI_RAGEXL
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select BOARD_ROMSIZE_KB_2048
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config MAINBOARD_DIR
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string
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default intel/jarrell
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config MAINBOARD_PART_NUMBER
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string
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default "Jarrell"
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 18
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config DIMM_MAP_LOGICAL
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hex
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default 0x0124
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endif # BOARD_INTEL_JARRELL
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@ -1,3 +0,0 @@
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Board name: Jarrell (SE7520JR2)
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Category: server
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Board URL: http://www.intel.com/support/motherboards/server/se7520jr2/
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@ -1,80 +0,0 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 376 r 0 reserved_memory
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376 1 e 1 power_up_watchdog
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 2 hyper_threading
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397 1 e 1 pxhd_bus_speed_100
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 983 984
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@ -1,262 +0,0 @@
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#include <spd.h>
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static void print_reg(unsigned char index)
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{
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unsigned char data;
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outb(index, 0x2e);
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data = inb(0x2f);
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print_debug("0x");
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print_debug_hex8(index);
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print_debug(": 0x");
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print_debug_hex8(data);
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print_debug("\n");
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return;
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}
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static void xbus_en(void)
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{
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/* select the XBUS function in the SIO */
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outb(0x07, 0x2e);
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outb(0x0f, 0x2f);
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outb(0x30, 0x2e);
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outb(0x01, 0x2f);
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return;
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}
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static void setup_func(unsigned char func)
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{
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/* select the function in the SIO */
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outb(0x07, 0x2e);
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outb(func, 0x2f);
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/* print out the regs */
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print_reg(0x30);
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print_reg(0x60);
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print_reg(0x61);
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print_reg(0x62);
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print_reg(0x63);
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print_reg(0x70);
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print_reg(0x71);
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print_reg(0x74);
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print_reg(0x75);
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return;
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}
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static void siodump(void)
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{
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int i;
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unsigned char data;
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print_debug("\n*** SERVER I/O REGISTERS ***\n");
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for (i=0x10; i<=0x2d; i++) {
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print_reg((unsigned char)i);
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}
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#if 0
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print_debug("\n*** XBUS REGISTERS ***\n");
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setup_func(0x0f);
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for (i=0xf0; i<=0xff; i++) {
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print_reg((unsigned char)i);
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}
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print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
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setup_func(0x03);
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print_reg(0xf0);
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print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
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setup_func(0x02);
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print_reg(0xf0);
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#endif
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print_debug("\n*** GPIO REGISTERS ***\n");
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setup_func(0x07);
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for (i=0xf0; i<=0xf8; i++) {
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print_reg((unsigned char)i);
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}
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print_debug("\n*** GPIO VALUES ***\n");
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data = inb(0x68a);
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print_debug("\nGPDO 4: 0x");
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print_debug_hex8(data);
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data = inb(0x68b);
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print_debug("\nGPDI 4: 0x");
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print_debug_hex8(data);
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print_debug("\n");
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#if 0
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print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
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setup_func(0x0a);
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print_reg(0xf0);
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print_debug("\n*** FAN CONTROL REGISTERS ***\n");
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setup_func(0x09);
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print_reg(0xf0);
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print_reg(0xf1);
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print_debug("\n*** RTC REGISTERS ***\n");
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setup_func(0x10);
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print_reg(0xf0);
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print_reg(0xf1);
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print_reg(0xf3);
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print_reg(0xf6);
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print_reg(0xf7);
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print_reg(0xfe);
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print_reg(0xff);
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print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
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setup_func(0x14);
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print_reg(0xf0);
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#endif
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return;
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}
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static void dump_bar14(unsigned dev)
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{
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int i;
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unsigned long bar;
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print_debug("BAR 14 Dump\n");
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bar = pci_read_config32(dev, 0x14);
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for(i = 0; i <= 0x300; i+=4) {
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#if 0
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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#endif
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if((i%4)==0) {
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print_debug("\n");
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print_debug_hex16(i);
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print_debug_char(' ');
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}
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print_debug_hex32(read32(bar + i));
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print_debug_char(' ');
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}
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print_debug("\n");
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}
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#if 0
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\n");
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}
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}
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}
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#endif
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void dump_spd_registers(void)
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{
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unsigned device;
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device = DIMM0;
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while(device <= DIMM7) {
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int status = 0;
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int i;
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print_debug("\n");
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print_debug("dimm ");
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print_debug_hex8(device);
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for(i = 0; (i < 256) ; i++) {
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unsigned char byte;
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if ((i % 16) == 0) {
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print_debug("\n");
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print_debug_hex8(i);
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print_debug(": ");
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}
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status = smbus_read_byte(device, i);
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if (status < 0) {
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print_debug("bad device: ");
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print_debug_hex8(-status);
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print_debug("\n");
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break;
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}
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print_debug_hex8(status);
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print_debug_char(' ');
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}
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device++;
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print_debug("\n");
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}
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}
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void dump_ipmi_registers(void)
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{
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unsigned device;
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device = 0x42;
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while(device <= 0x42) {
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int status = 0;
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int i;
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print_debug("\n");
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print_debug("ipmi ");
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print_debug_hex8(device);
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for(i = 0; (i < 8) ; i++) {
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unsigned char byte;
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status = smbus_read_byte(device, 2);
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if (status < 0) {
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print_debug("bad device: ");
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print_debug_hex8(-status);
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print_debug("\n");
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break;
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}
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print_debug_hex8(status);
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print_debug_char(' ');
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}
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device++;
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print_debug("\n");
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}
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}
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@ -1,80 +0,0 @@
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chip northbridge/intel/e7520
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device domain 0 on
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subsystemid 0x8086 0x1079 inherit
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 01.0 on end
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device pci 02.0 on
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chip southbridge/intel/pxhd # pxhd1
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 00.2 on
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chip drivers/generic/generic
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device pci 04.0 on end
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device pci 04.1 on end
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end
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end
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device pci 00.3 on end
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end
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end
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device pci 06.0 on end
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chip southbridge/intel/i82801ex # i82801er
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 off end
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device pci 1d.7 on end
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device pci 1e.0 on
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chip drivers/ati/ragexl
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device pci 0c.0 on end
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end
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end
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device pci 1f.0 on
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chip superio/nsc/pc87427
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device pnp 2e.0 off end
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device pnp 2e.2 on
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# io 0x60 = 0x2f8
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# irq 0x70 = 3
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on
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# io 0x60 = 0x3f8
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# irq 0x70 = 4
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.4 off end
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device pnp 2e.5 off end
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device pnp 2e.6 on
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end
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device pnp 2e.9 off end
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device pnp 2e.a off end
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device pnp 2e.f on end
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device pnp 2e.10 off end
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device pnp 2e.14 off end
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end
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end
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device pci 1f.1 on end
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device pci 1f.2 off end
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device pci 1f.3 on end
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device pci 1f.5 off end
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device pci 1f.6 off end
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register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
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register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
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register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
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end
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end
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device cpu_cluster 0 on
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chip cpu/intel/socket_mPGA604 # cpu 0
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device lapic 0 on end
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end
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chip cpu/intel/socket_mPGA604 # cpu 1
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device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x40114180 size = 320 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x24d0, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x38, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, 0xe8, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x02, 0x20, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x03, 0x28, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, 0x60, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x02, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x04, 0x00},
|
||||
{0x02, 0x10, {{0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x05, 0x00},
|
||||
{0x02, 0x18, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}}, 0x06, 0x00},
|
||||
{0x03, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x01, 0x00},
|
||||
{0x03, 0x10, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}}, 0x02, 0x00},
|
||||
{0x03, 0x18, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x03, 0x00},
|
||||
{0x00, 0x10, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, 0x18, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, 0x20, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, 0x28, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, 0x30, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, 0x38, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
#include <arch/io.h>
|
||||
|
||||
static void mch_reset(void)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev != PCI_DEV_INVALID) {
|
||||
/* I/O space is always enables */
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
|
||||
base = ICH5_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Set GPIO 19 mux to IO usage */
|
||||
value = inl(base);
|
||||
value |= (1 <<19);
|
||||
outl(value, base);
|
||||
|
||||
/* Pull GPIO 19 low */
|
||||
value = inl(base + 0x0c);
|
||||
value &= ~(1 << 19);
|
||||
outl(value, base + 0x0c);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void mainboard_set_e7520_pll(unsigned bits)
|
||||
{
|
||||
uint16_t gpio_index;
|
||||
uint8_t data;
|
||||
device_t dev;
|
||||
|
||||
/* currently only handle the Jarrell/PC87427 case */
|
||||
dev = PC87427_GPIO_DEV;
|
||||
|
||||
|
||||
pnp_set_logical_device(dev);
|
||||
gpio_index = pnp_read_iobase(dev, 0x60);
|
||||
|
||||
/* select SIO GPIO port 4, pin 2 */
|
||||
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
|
||||
/* set to push-pull, enable output */
|
||||
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
|
||||
|
||||
/* select SIO GPIO port 4, pin 4 */
|
||||
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
|
||||
/* set to push-pull, enable output */
|
||||
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
|
||||
|
||||
/* set gpio 42,44 signal levels */
|
||||
data = inb(gpio_index + PC87427_GPDO_4);
|
||||
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
|
||||
print_debug("set_pllsel: correct settings detected!\n");
|
||||
return; /* settings already configured */
|
||||
} else {
|
||||
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
|
||||
/* reset */
|
||||
print_debug("set_pllsel: settings adjusted, now resetting...\n");
|
||||
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
|
||||
// mch_reset();
|
||||
full_reset();
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void mainboard_set_e7520_leds(void)
|
||||
{
|
||||
uint8_t cnt;
|
||||
uint8_t data;
|
||||
device_t dev;
|
||||
|
||||
/* currently only handle the Jarrell/PC87427 case */
|
||||
dev = PC87427_GPIO_DEV;
|
||||
|
||||
pnp_set_logical_device(dev);
|
||||
|
||||
/* enable */
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
outb(0x2d, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
|
||||
/* Set auto mode for dimm leds and post */
|
||||
outb(0xf0,0x2e);
|
||||
outb(0x70,0x2f);
|
||||
outb(0xf4,0x2e);
|
||||
outb(0x30,0x2f);
|
||||
outb(0xf5,0x2e);
|
||||
outb(0x88,0x2f);
|
||||
outb(0xf6,0x2e);
|
||||
outb(0x00,0x2f);
|
||||
outb(0xf7,0x2e);
|
||||
outb(0x90,0x2f);
|
||||
outb(0xf8,0x2e);
|
||||
outb(0x00,0x2f);
|
||||
|
||||
/* Turn the leds off */
|
||||
outb(0x00,0x88);
|
||||
outb(0x00,0x90);
|
||||
|
||||
/* Disable the ports */
|
||||
outb(0xf5,0x2e);
|
||||
outb(0x00,0x2f);
|
||||
outb(0xf7,0x2e);
|
||||
outb(0x00,0x2f);
|
||||
outb(0xf4,0x2e);
|
||||
outb(0x00,0x2f);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -1,238 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_pxhd_3 = 0;
|
||||
unsigned char bus_pxhd_4 = 0;
|
||||
unsigned char bus_pxhd_x = 0;
|
||||
unsigned char bus_ich5r_1;
|
||||
unsigned int bus_pxhd_id;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* ich5r */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
|
||||
|
||||
bus_ich5r_1 = 4;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
|
||||
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
/* test for active riser with 2nd pxh device */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
|
||||
if (dev) {
|
||||
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(bus_pxhd_id == 0x35998086) {
|
||||
bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
/* pxhd-3 */
|
||||
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(bus_pxhd_id == 0x03298086) {
|
||||
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
/* pxhd-4 */
|
||||
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(bus_pxhd_id == 0x032a8086) {
|
||||
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* pxhd apic 3 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x09, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
}
|
||||
/* pxhd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x0a, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
}
|
||||
|
||||
/* pxhd apic 5 */
|
||||
if(bus_pxhd_3) { /* Active riser pxhd */
|
||||
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x0b, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
|
||||
}
|
||||
}
|
||||
/* pxhd apic 6 */
|
||||
if(bus_pxhd_4) { /* active riser pxhd */
|
||||
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x0c, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0a, 0x08, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0b, 0x08, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0a, 0x08, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x07, 0x08, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0b, 0x08, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x05, 0x08, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0b, 0x08, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x07, 0x08, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0b, 0x08, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_isa, 0x0a, 0x08, 0x10);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
|
||||
/* FIXME verify I have the irqs handled for all of the risers */
|
||||
|
||||
/* 2:3.0 PCI Slot 1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
|
||||
|
||||
|
||||
/* 3:7.0 PCI Slot 2 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
|
||||
|
||||
/* PCI Slot 3 (if active riser) */
|
||||
if(bus_pxhd_3) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
|
||||
}
|
||||
|
||||
/* PCI Slot 4 (if active riser) */
|
||||
if(bus_pxhd_4) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
|
||||
}
|
||||
|
||||
/* Onboard SCSI 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
|
||||
|
||||
/* Onboard SCSI 1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
|
||||
|
||||
/* Onboard NIC 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
|
||||
|
||||
/* Onboard NIC 1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
|
||||
|
||||
/* Onboard VGA */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
void full_reset(void)
|
||||
{
|
||||
/* Enable power on after power fail... */
|
||||
unsigned byte;
|
||||
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
|
||||
byte &= 0xfe;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
|
||||
|
||||
outb(0x0e, 0xcf9);
|
||||
}
|
||||
|
||||
static void power_down_reset_check(void)
|
||||
{
|
||||
uint8_t cmos;
|
||||
|
||||
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
|
||||
print_debug("Boot byte = ");
|
||||
print_debug_hex8(cmos);
|
||||
print_debug("\n");
|
||||
|
||||
if((cmos>2)&&(cmos&1)) full_reset();
|
||||
}
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801ex/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "superio/nsc/pc87427/pc87427.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/i82801ex/reset.c"
|
||||
#include "power_reset_check.c"
|
||||
#include "jarrell_fixups.c"
|
||||
#include "superio/nsc/pc87427/early_init.c"
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
#include "lib/debug.c" // XXX
|
||||
|
||||
#define SIO_GPIO_BASE 0x680
|
||||
#define SIO_XBUS_BASE 0x4880
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
|
||||
|
||||
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
|
||||
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
/* Setup the console */
|
||||
pc87427_disable_dev(CONSOLE_SERIAL_DEV);
|
||||
pc87427_disable_dev(HIDDEN_SERIAL_DEV);
|
||||
pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
/* Enable Serial 2 lines instead of GPIO */
|
||||
outb(0x2c, 0x2e);
|
||||
outb((inb(0x2f) & (~1<<1)), 0x2f);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
|
||||
|
||||
pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
|
||||
xbus_cfg(PC87427_XBUS_DEV);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing ich5?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
enable_smbus();
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
power_down_reset_check();
|
||||
// dump_ipmi_registers();
|
||||
mainboard_set_e7520_leds();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
ich5_watchdog_on();
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
/* NOTE: ROMCC dies with an internal compiler error if the
|
||||
* following line is removed.
|
||||
*/
|
||||
print_debug("SDRAM is up.\n");
|
||||
}
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
}
|
||||
|
||||
static void disable_ich5_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_jarell_frb3(void)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 0);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
|
||||
base = ICH5_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Configure GPIO 48 and 40 as GPIO */
|
||||
value = inl(base + 0x30);
|
||||
value |= (1 << 16) | ( 1 << 8);
|
||||
outl(value, base + 0x30);
|
||||
|
||||
/* Configure GPIO 48 as Output */
|
||||
value = inl(base + 0x34);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x34);
|
||||
|
||||
/* Toggle GPIO 48 high to low */
|
||||
value = inl(base + 0x38);
|
||||
value |= (1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_ich5_watchdog();
|
||||
disable_jarell_frb3();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
||||
static void ich5_watchdog_on(void)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
unsigned char byte;
|
||||
|
||||
/* check cmos options */
|
||||
byte = cmos_read(RTC_BOOT_BYTE-1);
|
||||
if(!(byte & 1)) return; /* no boot watchdog */
|
||||
byte = cmos_read(RTC_BOOT_BYTE);
|
||||
if(!(byte & 2)) return; /* fallback so ignore */
|
||||
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
|
||||
/* set the time value 1 cnt = .6 sec */
|
||||
outw(0x0010, base + 0x01);
|
||||
/* reload the timer with the value */
|
||||
outw(0x0001, base + 0x00);
|
||||
|
||||
/* clear bit 11 in TCO1_CNT to start watchdog */
|
||||
value = inw(base + 0x08);
|
||||
value &= ~(1 << 11);
|
||||
outw(value, base + 0x08);
|
||||
|
||||
print_debug("Watchdog ICH5 enabled\n");
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_INTEL_XE7501DEVKIT
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7501
|
||||
select SOUTHBRIDGE_INTEL_I82870
|
||||
select SOUTHBRIDGE_INTEL_I82801CX
|
||||
select SUPERIO_SMSC_LPC47B272
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select UDELAY_TSC
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default intel/xe7501devkit
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "XE7501devkit"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 12
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_INTEL_XE7501DEVKIT
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* Ported to Intel XE7501DEVKIT from Agami Aruma
|
||||
* written by Stefan Reinauer <stepan@openbios.org>
|
||||
* (C) 2005 Stefan Reinauer
|
||||
* (C) 2005 Digital Design Corporation
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <assert.h>
|
||||
#include "bus.h"
|
||||
#include "ioapic.h"
|
||||
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_srat(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
unsigned int irq_start = 0;
|
||||
device_t dev = 0;
|
||||
struct resource* res = NULL;
|
||||
|
||||
|
||||
// SJM: Hard-code CPU LAPIC entries for now
|
||||
// Use SourcePoint numbering of processors
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
|
||||
|
||||
|
||||
// Southbridge IOAPIC
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, IO_APIC_ADDR, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#2 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#2 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
|
||||
// P64H2#1 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#1 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// Map ISA IRQ 0 to IRQ 2
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
|
||||
|
||||
// IRQ9 differs from ISA standard - ours is active high, level-triggered
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
Category: eval
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#ifndef XE7501DEVKIT_BUS_H_INCLUDED
|
||||
#define XE7501DEVKIT_BUS_H_INCLUDED
|
||||
|
||||
// These were determined by seeing how coreboot enumerates the various
|
||||
// PCI (and PCI-like) buses on the board.
|
||||
|
||||
#define PCI_BUS_CHIPSET 0
|
||||
#define PCI_BUS_E7501_HI_B 1 // P64H2#2
|
||||
#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
|
||||
#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
|
||||
#define PCI_BUS_E7501_HI_D 4 // P64H2#1
|
||||
#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
|
||||
#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
|
||||
#define PCI_BUS_ICH3 7 // ICH3-S
|
||||
|
||||
#endif // XE7501DEVKIT_BUS_H_INCLUDED
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
chip northbridge/intel/e7501
|
||||
device domain 0 on
|
||||
subsystemid 0x8086 0x2480 inherit
|
||||
device pci 0.0 on end # Chipset host controller
|
||||
device pci 0.1 on end # Host RASUM controller
|
||||
device pci 2.0 on # Hub interface B
|
||||
chip southbridge/intel/i82870 # P64H2
|
||||
device pci 1c.0 on end # IOAPIC - bus B
|
||||
device pci 1d.0 on end # Hub to PCI-B bridge
|
||||
device pci 1e.0 on end # IOAPIC - bus A
|
||||
device pci 1f.0 on end # Hub to PCI-A bridge
|
||||
end
|
||||
end
|
||||
device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
|
||||
device pci 4.0 on # Hub interface D
|
||||
chip southbridge/intel/i82870 # P64H2
|
||||
device pci 1c.0 on end # IOAPIC - bus B
|
||||
device pci 1d.0 on end # Hub to PCI-B bridge
|
||||
device pci 1e.0 on end # IOAPIC - bus A
|
||||
device pci 1f.0 on end # Hub to PCI-A bridge
|
||||
end
|
||||
end
|
||||
device pci 6.0 on end # E7501 Power management registers? (undocumented)
|
||||
chip southbridge/intel/i82801cx
|
||||
device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
|
||||
device pci 1d.1 off end # USB (not populated)
|
||||
device pci 1d.2 off end # USB (not populated)
|
||||
device pci 1e.0 on # Hub to PCI bridge
|
||||
device pci 0.0 on end
|
||||
end
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/smsc/lpc47b272
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Keyboard interrupt
|
||||
irq 0x72 = 12 # Mouse interrupt
|
||||
end
|
||||
device pnp 2e.a off end # ACPI
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end # AC97 Audio
|
||||
device pci 1f.6 off end # AC97 Modem
|
||||
end # SB
|
||||
end # PCI domain
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* This is a dummy dsdt. Normal ACPI requires a DSDT, but in this case, ACPI
|
||||
is just a workaround for QNX. It would be nice to eventually have a real
|
||||
dsdt here.
|
||||
Note: It will not be hooked up at runtime. It won't even get linked.
|
||||
But we still need this file. */
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv2", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20090419 // OEM revision
|
||||
)
|
||||
{
|
||||
}
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
/* FIXME: This needs to go into a separate .h file
|
||||
* to be included by the ich7 smi handler, ich7 smi init
|
||||
* code and the mainboard fadt.
|
||||
*/
|
||||
#define APM_CNT 0x0 /* ACPI mode only */
|
||||
#define CST_CONTROL 0x85
|
||||
#define PST_CONTROL 0x0
|
||||
#define ACPI_DISABLE 0xAA
|
||||
#define ACPI_ENABLE 0x55
|
||||
#define S4_BIOS 0x77
|
||||
#define GNVS_UPDATE 0xea
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 4;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = 0; /* PM_MOBILE; */
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = ACPI_ENABLE;
|
||||
fadt->acpi_disable = ACPI_DISABLE;
|
||||
fadt->s4bios_req = S4_BIOS;
|
||||
fadt->pstate_cnt = PST_CONTROL;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = 0x0;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x28;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0; /* CST_CONTROL; */
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 85;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = 0x03;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 0;
|
||||
fadt->reset_reg.bit_width = 0;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0x0;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 0;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 64;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
// IOAPIC addresses determined by coreboot enumeration.
|
||||
// Someday add functions to get APIC IDs and versions from the chips themselves.
|
||||
|
||||
#define IOAPIC_ICH3 2
|
||||
#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010
|
||||
#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010
|
||||
#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010
|
||||
#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010
|
||||
|
||||
#define P64H2_IOAPIC_VERSION 0x20
|
||||
#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
/* Run checkpir to verify any changes to this table...
|
||||
Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "bus.h"
|
||||
|
||||
#define UNUSED_INTERRUPT {0, 0}
|
||||
#define PIRQ_A 0x60
|
||||
#define PIRQ_B 0x61
|
||||
#define PIRQ_C 0x62
|
||||
#define PIRQ_D 0x63
|
||||
#define PIRQ_E 0x68
|
||||
#define PIRQ_F 0x69
|
||||
#define PIRQ_G 0x6A
|
||||
#define PIRQ_H 0x6B
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes
|
||||
0, // PCI bus number on which the interrupt router resides
|
||||
PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
|
||||
0, // PCI-exclusive IRQ bitmap
|
||||
PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
|
||||
PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router
|
||||
0, // Additional miniport information
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
|
||||
0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
|
||||
{
|
||||
// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
|
||||
// This was determined from linux-2.6.11/arch/x86/pci/irq.c
|
||||
// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
|
||||
// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
|
||||
// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
|
||||
|
||||
// INTA# INTB# INTC# INTD#
|
||||
// bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
|
||||
|
||||
{PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
|
||||
{PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
|
||||
|
||||
// P64H2#2 Bus A
|
||||
{PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#2 Bus B
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#1 Bus A
|
||||
{PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#1 Bus B
|
||||
{PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet
|
||||
{PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// ICH-3 PCI bus
|
||||
{PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video
|
||||
{PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,142 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include "bus.h"
|
||||
#include "ioapic.h"
|
||||
|
||||
// Generate MP-table IRQ numbers for PCI devices.
|
||||
#define INT_A 0
|
||||
#define INT_B 1
|
||||
#define INT_C 2
|
||||
#define INT_D 3
|
||||
#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
|
||||
|
||||
static int bus_isa;
|
||||
|
||||
static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
||||
// TODO: Gack. This is REALLY ugly.
|
||||
|
||||
// Southbridge IOAPIC
|
||||
smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR); // APIC ID, Version, Address
|
||||
|
||||
// P64H2#2 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
// P64H2#2 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
|
||||
// P64H2#1 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
// P64H2#1 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG();
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
|
||||
}
|
||||
|
||||
static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
|
||||
{
|
||||
// Chipset PCI bus
|
||||
// Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
|
||||
mptable_lintsrc(mc, PCI_BUS_CHIPSET);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
|
||||
|
||||
// P64H2#2 Bus B
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
|
||||
|
||||
// P64H2#2 Bus A
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
|
||||
|
||||
// P64H2#1 Bus B
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
|
||||
|
||||
// P64H2#1 Bus A
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
|
||||
|
||||
// ICH-3
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)
|
||||
|
||||
// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void* v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
xe7501devkit_register_ioapics(mc);
|
||||
xe7501devkit_register_interrupts(mc);
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <stdlib.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801cx/early_smbus.c"
|
||||
#include "northbridge/intel/e7501/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/intel/e7501/debug.c"
|
||||
#include "superio/smsc/lpc47b272/early_serial.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7501/raminit.c"
|
||||
#include "northbridge/intel/e7501/reset_test.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
// This function MUST appear last (ROMCC limitation)
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.d0f1 = PCI_DEV(0, 0, 1),
|
||||
.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
|
||||
.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
// Skip this if there was a built in self test failure
|
||||
early_mtrr_init();
|
||||
enable_lapic();
|
||||
}
|
||||
|
||||
// Get the serial port running and print a welcome banner
|
||||
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
// Halt if there was a built in self test failure
|
||||
report_bist_failure(bist);
|
||||
|
||||
// print_pci_devices();
|
||||
|
||||
// If this is a warm boot, some initialization can be skipped
|
||||
|
||||
if (!bios_reset_detected())
|
||||
{
|
||||
enable_smbus();
|
||||
// dump_spd_registers(&memctrl[0]);
|
||||
// dump_smbus_registers();
|
||||
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
|
||||
}
|
||||
|
||||
// NOTE: ROMCC dies with an internal compiler error
|
||||
// if the following line is removed.
|
||||
print_debug("SDRAM is up.\n");
|
||||
}
|
||||
|
|
@ -17,16 +17,6 @@ config BOARD_SUPERMICRO_H8SCM
|
|||
bool "H8SCM"
|
||||
config BOARD_SUPERMICRO_H8QGI
|
||||
bool "H8QGI"
|
||||
config BOARD_SUPERMICRO_X6DAI_G
|
||||
bool "X6DAi-G"
|
||||
config BOARD_SUPERMICRO_X6DHE_G2
|
||||
bool "X6DHE-G2"
|
||||
config BOARD_SUPERMICRO_X6DHE_G
|
||||
bool "X6DHE-G"
|
||||
config BOARD_SUPERMICRO_X6DHR_IG2
|
||||
bool "X6DHR-iG2"
|
||||
config BOARD_SUPERMICRO_X6DHR_IG
|
||||
bool "X6DHR-iG"
|
||||
config BOARD_SUPERMICRO_X7DB8
|
||||
bool "X7DB8 / X7DB8+"
|
||||
|
||||
|
|
@ -39,11 +29,6 @@ source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
|
|||
source "src/mainboard/supermicro/h8scm_fam10/Kconfig"
|
||||
source "src/mainboard/supermicro/h8scm/Kconfig"
|
||||
source "src/mainboard/supermicro/h8qgi/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dai_g/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhe_g/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
|
||||
source "src/mainboard/supermicro/x7db8/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
if BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7525
|
||||
select SOUTHBRIDGE_INTEL_ESB6300
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select ROMCC
|
||||
select HAVE_HARD_RESET
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dai_g
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DAi-G"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
|
||||
endif # BOARD_SUPERMICRO_X6DAI_G
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#include <spd.h>
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\n*** SERVER I/O REGISTERS ***\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\n*** XBUS REGISTERS ***\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\n*** GPIO REGISTERS ***\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\n*** GPIO VALUES ***\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\n*** RTC REGISTERS ***\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = DIMM0;
|
||||
while(device <= DIMM7) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
chip northbridge/intel/e7525 # mch
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x6780 inherit
|
||||
chip southbridge/intel/esb6300 # esb6300
|
||||
register "pirq_a_d" = "0x0b0a0a05"
|
||||
register "pirq_e_h" = "0x0a0b0c80"
|
||||
|
||||
device pci 1c.0 on end
|
||||
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.4 on end
|
||||
device pci 1d.5 on end
|
||||
device pci 1d.7 on end
|
||||
|
||||
device pci 1e.0 on end
|
||||
|
||||
device pci 1f.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.1 off end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a on end
|
||||
device pnp 2e.b off end
|
||||
device pnp 2e.f off end
|
||||
device pnp 2e.10 off end
|
||||
device pnp 2e.14 off end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end
|
||||
device pci 1f.2 on end
|
||||
device pci 1f.3 on end
|
||||
device pci 1f.5 off end
|
||||
device pci 1f.6 on end
|
||||
end
|
||||
device pci 00.0 on end
|
||||
device pci 00.1 on end
|
||||
device pci 00.2 on end
|
||||
device pci 02.0 on end
|
||||
device pci 03.0 on end
|
||||
device pci 04.0 on end
|
||||
device pci 08.0 on end
|
||||
end
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x40163ed0 size = 272 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x122e, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x78, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, 0x00, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0x10, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00},
|
||||
{0x01, 0x00, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x04, 0x00},
|
||||
{0x00, 0x20, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00},
|
||||
{0x02, 0x00, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x06, 0x00},
|
||||
{0x00, 0xe0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00},
|
||||
{0x04, 0x08, {{0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}}, 0x01, 0x00},
|
||||
{0x04, 0x10, {{0x6a, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x07, 0x00},
|
||||
{0x04, 0x18, {{0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}, {0x6a, 0x1ef8}}, 0x02, 0x00},
|
||||
{0x00, 0xf0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00},
|
||||
{0x05, 0x40, {{0x68, 0x1ef8}, {0x69, 0x1ef8}, {0x6a, 0x1ef8}, {0x6b, 0x1ef8}}, 0x03, 0x00},
|
||||
{0x05, 0x18, {{0x6a, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x08, 0x00},
|
||||
{0x05, 0x10, {{0x69, 0x1ef8}, {0x6a, 0x1ef8}, {0x6b, 0x1ef8}, {0x68, 0x1ef8}}, 0x05, 0x00},
|
||||
{0x00, 0xf8, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00},
|
||||
{0x00, 0xe8, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x6b, 0x1ef8}}, 0x00, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_6300;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* southbridge */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
bus_6300 = 5;
|
||||
}
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
/* Slot 1 function 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
4, 0x04, 0x03, 0x00);
|
||||
/* Slot 2 function 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
4, 0x0c, 0x03, 0x01);
|
||||
/* Slot 3 function 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_6300, 0x20, 0x02, 0x14);
|
||||
/* Slot 4 function 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_6300, 0x08, 0x02, 0x15);
|
||||
/* On board NIC */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_6300, 0x0c, 0x02, 0x16);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
// smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
// bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "drivers/pc80/udelay_io.c"
|
||||
#include "lib/delay.c"
|
||||
#include "southbridge/intel/esb6300/early_smbus.c"
|
||||
#include "northbridge/intel/e7525/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "lib/debug.c" // XXX
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/esb6300/reset.c"
|
||||
#include "superio/winbond/w83627hf/early_serial.c"
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include "northbridge/intel/e7525/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
|
||||
#define DUMMY_DEV PNP_DEV(0x2e, 0)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7525/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x00, 0),
|
||||
.f1 = PCI_DEV(0, 0x00, 1),
|
||||
.f2 = PCI_DEV(0, 0x00, 2),
|
||||
.f3 = PCI_DEV(0, 0x00, 3),
|
||||
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
|
||||
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
w83627hf_set_clksel_48(DUMMY_DEV);
|
||||
w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing 6300ESB?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 1
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
// dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_esb6300_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing 6300ESB?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
disable_esb6300_watchdog();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_ESB6300
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select ROMCC
|
||||
select HAVE_HARD_RESET
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhe_g
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHE-G"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
|
||||
endif # BOARD_SUPERMICRO_X6DHE_G
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#include <spd.h>
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\n*** SERVER I/O REGISTERS ***\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\n*** XBUS REGISTERS ***\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\n*** GPIO REGISTERS ***\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\n*** GPIO VALUES ***\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\n*** RTC REGISTERS ***\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = DIMM0;
|
||||
while(device <= DIMM7) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
chip northbridge/intel/e7520 # MCH
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x6080 inherit
|
||||
chip southbridge/intel/esb6300 # ESB6300
|
||||
register "pirq_a_d" = "0x0b070a05"
|
||||
register "pirq_e_h" = "0x0a808080"
|
||||
|
||||
device pci 1c.0 on
|
||||
chip drivers/generic/generic
|
||||
device pci 01.0 on end # onboard gige1
|
||||
device pci 02.0 on end # onboard gige2
|
||||
end
|
||||
end
|
||||
|
||||
# USB ports
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.4 on end # Southbridge Watchdog timer
|
||||
device pci 1d.5 on end # Southbridge I/O apic1
|
||||
device pci 1d.7 on end
|
||||
|
||||
# VGA / PCI 32-bit
|
||||
device pci 1e.0 on
|
||||
chip drivers/generic/generic
|
||||
device pci 01.0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
device pci 1f.0 on # ISA bridge
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a on end
|
||||
device pnp 2e.b off end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end
|
||||
device pci 1f.2 off end
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end
|
||||
device pci 1f.6 off end
|
||||
end
|
||||
|
||||
device pci 00.0 on end # Northbridge
|
||||
device pci 00.1 on end # Northbridge Error reporting
|
||||
device pci 01.0 on end
|
||||
device pci 02.0 on
|
||||
chip southbridge/intel/pxhd # PXHD 6700
|
||||
device pci 00.0 on end # bridge
|
||||
device pci 00.1 on end # I/O apic
|
||||
device pci 00.2 on end # bridge
|
||||
device pci 00.3 on end # I/O apic
|
||||
end
|
||||
end
|
||||
# device register "intrline" = "0x00070105"
|
||||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # CPU 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # CPU 1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x25a1, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc4, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00},
|
||||
{0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_esb6300_1;
|
||||
unsigned char bus_esb6300_2;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* esb6300_2 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
|
||||
bus_esb6300_1 = 6;
|
||||
}
|
||||
/* esb6300_1 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
bus_esb6300_2 = 7;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* PXHd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
|
||||
}
|
||||
/* PXHd apic 5 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x05, 0x20, res->base);
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
0x03, 0x08, 0x05, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
0x03, 0x08, 0x05, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_1, 0x04, 0x03, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_1, 0x08, 0x03, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_2, 0x04, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_2, 0x08, 0x02, 0x14);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
|
||||
/* FIXME verify I have the irqs handled for all of the risers */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "drivers/pc80/udelay_io.c"
|
||||
#include "lib/delay.c"
|
||||
#include "southbridge/intel/esb6300/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "lib/debug.c" // XXX
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/esb6300/reset.c"
|
||||
#include "superio/winbond/w83627hf/early_serial.c"
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
|
||||
#define DUMMY_DEV PNP_DEV(0x2e, 0)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static void mch_reset(void) {}
|
||||
static void mainboard_set_e7520_pll(unsigned bits) {}
|
||||
static void mainboard_set_e7520_leds(void) {}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
|
||||
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
w83627hf_set_clksel_48(DUMMY_DEV);
|
||||
w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing esb6300?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
// mainboard_set_e7520_leds();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ESB6300_WDBASE 0x400
|
||||
#define ESB6300_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_esb6300_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing esb6300?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ESB6300_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_jarell_frb3(void)
|
||||
{
|
||||
#if 0
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing esb6300?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 0);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ESB6300_GPIOBASE | 1);
|
||||
base = ESB6300_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Configure GPIO 48 and 40 as GPIO */
|
||||
value = inl(base + 0x30);
|
||||
value |= (1 << 16) | ( 1 << 8);
|
||||
outl(value, base + 0x30);
|
||||
|
||||
/* Configure GPIO 48 as Output */
|
||||
value = inl(base + 0x34);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x34);
|
||||
|
||||
/* Toggle GPIO 48 high to low */
|
||||
value = inl(base + 0x38);
|
||||
value |= (1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_esb6300_watchdog();
|
||||
// disable_jarell_frb3();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801EX
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_NSC_PC87427
|
||||
select ROMCC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select USE_WATCHDOG_ON_BOOT
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhe_g2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHE-G2"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
|
||||
endif # BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHE-G2.cfm
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#include <spd.h>
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\n*** SERVER I/O REGISTERS ***\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\n*** XBUS REGISTERS ***\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\n*** GPIO REGISTERS ***\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\n*** GPIO VALUES ***\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\n*** RTC REGISTERS ***\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = DIMM0;
|
||||
while(device <= DIMM7) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
chip northbridge/intel/e7520 # MCH
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x6080 inherit
|
||||
chip southbridge/intel/i82801ex # ICH5R
|
||||
register "pirq_a_d" = "0x0b070a05"
|
||||
register "pirq_e_h" = "0x0a808080"
|
||||
|
||||
device pci 1c.0 on
|
||||
chip drivers/generic/generic
|
||||
device pci 01.0 on end # onboard gige1
|
||||
device pci 02.0 on end # onboard gige2
|
||||
end
|
||||
end
|
||||
|
||||
# USB ports
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.4 on end # Southbridge Watchdog timer
|
||||
device pci 1d.5 on end # Southbridge I/O apic1
|
||||
device pci 1d.7 on end
|
||||
|
||||
# VGA / PCI 32-bit
|
||||
device pci 1e.0 on
|
||||
chip drivers/generic/generic
|
||||
device pci 01.0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
device pci 1f.0 on # ISA bridge
|
||||
chip superio/nsc/pc87427
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a on end
|
||||
device pnp 2e.b off end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end
|
||||
device pci 1f.2 on end
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end
|
||||
device pci 1f.6 off end
|
||||
end
|
||||
|
||||
device pci 00.0 on end # Northbridge
|
||||
device pci 00.1 on end # Northbridge Error reporting
|
||||
device pci 01.0 on end
|
||||
device pci 02.0 on
|
||||
chip southbridge/intel/pxhd # PXHD 6700
|
||||
device pci 00.0 on end # bridge
|
||||
device pci 00.1 on end # I/O apic
|
||||
device pci 00.2 on end # bridge
|
||||
device pci 00.3 on end # I/O apic
|
||||
end
|
||||
end
|
||||
# device register "intrline" = "0x00070105"
|
||||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # CPU 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # CPU 1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x25a1, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc4, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00},
|
||||
{0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_esb6300_1;
|
||||
unsigned char bus_esb6300_2;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* esb6300_2 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
|
||||
bus_esb6300_1 = 6;
|
||||
}
|
||||
/* esb6300_1 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
bus_esb6300_2 = 7;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* PXHd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
|
||||
}
|
||||
/* PXHd apic 5 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x05, 0x20, res->base);
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
0x03, 0x08, 0x05, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
0x03, 0x08, 0x05, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_1, 0x04, 0x03, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_1, 0x08, 0x03, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_2, 0x04, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
|
||||
bus_esb6300_2, 0x08, 0x02, 0x14);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
|
||||
/* FIXME verify I have the irqs handled for all of the risers */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801ex/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "superio/nsc/pc87427/pc87427.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "lib/debug.c" // XXX
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/i82801ex/reset.c"
|
||||
#include "superio/nsc/pc87427/early_init.c"
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static void mch_reset(void) {}
|
||||
static void mainboard_set_e7520_pll(unsigned bits) {}
|
||||
static void mainboard_set_e7520_leds(void) {}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
|
||||
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
/* Setup the console */
|
||||
outb(0x87,0x2e);
|
||||
outb(0x87,0x2e);
|
||||
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
|
||||
pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing ich5r?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
// mainboard_set_e7520_leds();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
//dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ESB6300_WDBASE 0x400
|
||||
#define ESB6300_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_esb6300_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing esb6300?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ESB6300_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_jarell_frb3(void)
|
||||
{
|
||||
#if 0
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing esb6300?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 0);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ESB6300_GPIOBASE | 1);
|
||||
base = ESB6300_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Configure GPIO 48 and 40 as GPIO */
|
||||
value = inl(base + 0x30);
|
||||
value |= (1 << 16) | ( 1 << 8);
|
||||
outl(value, base + 0x30);
|
||||
|
||||
/* Configure GPIO 48 as Output */
|
||||
value = inl(base + 0x34);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x34);
|
||||
|
||||
/* Toggle GPIO 48 high to low */
|
||||
value = inl(base + 0x38);
|
||||
value |= (1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_esb6300_watchdog();
|
||||
// disable_jarell_frb3();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801EX
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select ROMCC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select USE_WATCHDOG_ON_BOOT
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhr_ig
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHR-iG"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
|
||||
endif # BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG.cfm
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#include <spd.h>
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\n*** SERVER I/O REGISTERS ***\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\n*** XBUS REGISTERS ***\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\n*** GPIO REGISTERS ***\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\n*** GPIO VALUES ***\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\n*** RTC REGISTERS ***\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = DIMM0;
|
||||
while(device <= DIMM7) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
chip northbridge/intel/e7520 # mch
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x5580 inherit
|
||||
chip southbridge/intel/i82801ex # i82801er
|
||||
# USB ports
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.2 on end
|
||||
device pci 1d.3 on end
|
||||
device pci 1d.7 on end
|
||||
|
||||
# -> VGA
|
||||
device pci 1e.0 on end
|
||||
|
||||
# -> IDE
|
||||
device pci 1f.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a on end
|
||||
device pnp 2e.b off end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end
|
||||
device pci 1f.2 on end
|
||||
device pci 1f.3 on end
|
||||
|
||||
register "pirq_a_d" = "0x0b070a05"
|
||||
register "pirq_e_h" = "0x0a808080"
|
||||
end
|
||||
device pci 00.0 on end
|
||||
device pci 00.1 on end
|
||||
device pci 01.0 on end
|
||||
device pci 02.0 on end
|
||||
device pci 03.0 on
|
||||
chip southbridge/intel/pxhd # pxhd1
|
||||
# Bus bridges and ioapics usually bus 2
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on
|
||||
# On board gig e1000
|
||||
chip drivers/generic/generic
|
||||
device pci 02.0 on end
|
||||
device pci 02.1 on end
|
||||
end
|
||||
end
|
||||
device pci 0.3 on end
|
||||
end
|
||||
end
|
||||
device pci 04.0 on
|
||||
chip southbridge/intel/pxhd # pxhd2
|
||||
# Bus bridges and ioapics usually bus 5
|
||||
device pci 0.0 on end
|
||||
# Slot 6 is usually 6:2.0
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
# Slot 7 is usually 7:2.0
|
||||
device pci 0.3 on end
|
||||
end
|
||||
end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070105"
|
||||
end
|
||||
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x24d0, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc4, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00},
|
||||
{0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_pxhd_3;
|
||||
unsigned char bus_pxhd_4;
|
||||
unsigned char bus_ich5r_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* ich5r */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
|
||||
|
||||
bus_ich5r_1 = 9;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(2, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
|
||||
|
||||
bus_pxhd_1 = 3;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(2, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_pxhd_2 = 4;
|
||||
}
|
||||
|
||||
/* pxhd-3 */
|
||||
dev = dev_find_slot(5, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
|
||||
|
||||
bus_pxhd_3 = 6;
|
||||
}
|
||||
/* pxhd-4 */
|
||||
dev = dev_find_slot(5, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_pxhd_4 = 7;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* pxhd apic 3 */
|
||||
dev = dev_find_slot(2, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.1\n");
|
||||
}
|
||||
/* pxhd apic 4 */
|
||||
dev = dev_find_slot(2, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.3\n");
|
||||
}
|
||||
/* pxhd apic 5 */
|
||||
dev = dev_find_slot(5, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x05, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.1\n");
|
||||
}
|
||||
/* pxhd apic 8 */
|
||||
dev = dev_find_slot(5, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x08, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.3\n");
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x76, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_2, 0x08, 0x04, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_2, 0x09, 0x04, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_3, 0x08, 0x05, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_4, 0x08, 0x08, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
(bus_isa - 1), 0x04, 0x02, 0x10);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801ex/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "lib/debug.c" // XXX
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/i82801ex/reset.c"
|
||||
#include "superio/winbond/w83627hf/early_serial.c"
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
|
||||
#define DUMMY_DEV PNP_DEV(0x2e, 0)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D0F0 | \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static void mch_reset(void) {}
|
||||
static void mainboard_set_e7520_pll(unsigned bits) {}
|
||||
static void mainboard_set_e7520_leds(void) {}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
|
||||
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
w83627hf_set_clksel_48(DUMMY_DEV);
|
||||
w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing ich5?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
mainboard_set_e7520_leds();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 1
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_ich5_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_jarell_frb3(void)
|
||||
{
|
||||
#if 0
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 0);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
|
||||
base = ICH5_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Configure GPIO 48 and 40 as GPIO */
|
||||
value = inl(base + 0x30);
|
||||
value |= (1 << 16) | ( 1 << 8);
|
||||
outl(value, base + 0x30);
|
||||
|
||||
/* Configure GPIO 48 as Output */
|
||||
value = inl(base + 0x34);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x34);
|
||||
|
||||
/* Toggle GPIO 48 high to low */
|
||||
value = inl(base + 0x38);
|
||||
value |= (1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_ich5_watchdog();
|
||||
// disable_jarell_frb3();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
if BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801EX
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select ROMCC
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select USE_WATCHDOG_ON_BOOT
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhr_ig2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHR-iG2"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
|
||||
endif # BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: server
|
||||
Board URL: http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG2.cfm
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 2 hyper_threading
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#include <spd.h>
|
||||
|
||||
static void print_reg(unsigned char index)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
outb(index, 0x2e);
|
||||
data = inb(0x2f);
|
||||
print_debug("0x");
|
||||
print_debug_hex8(index);
|
||||
print_debug(": 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static void xbus_en(void)
|
||||
{
|
||||
/* select the XBUS function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(0x0f, 0x2f);
|
||||
outb(0x30, 0x2e);
|
||||
outb(0x01, 0x2f);
|
||||
return;
|
||||
}
|
||||
|
||||
static void setup_func(unsigned char func)
|
||||
{
|
||||
/* select the function in the SIO */
|
||||
outb(0x07, 0x2e);
|
||||
outb(func, 0x2f);
|
||||
/* print out the regs */
|
||||
print_reg(0x30);
|
||||
print_reg(0x60);
|
||||
print_reg(0x61);
|
||||
print_reg(0x62);
|
||||
print_reg(0x63);
|
||||
print_reg(0x70);
|
||||
print_reg(0x71);
|
||||
print_reg(0x74);
|
||||
print_reg(0x75);
|
||||
return;
|
||||
}
|
||||
|
||||
static void siodump(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char data;
|
||||
|
||||
print_debug("\n*** SERVER I/O REGISTERS ***\n");
|
||||
for (i=0x10; i<=0x2d; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
#if 0
|
||||
print_debug("\n*** XBUS REGISTERS ***\n");
|
||||
setup_func(0x0f);
|
||||
for (i=0xf0; i<=0xff; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
|
||||
print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x03);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
|
||||
setup_func(0x02);
|
||||
print_reg(0xf0);
|
||||
|
||||
#endif
|
||||
print_debug("\n*** GPIO REGISTERS ***\n");
|
||||
setup_func(0x07);
|
||||
for (i=0xf0; i<=0xf8; i++) {
|
||||
print_reg((unsigned char)i);
|
||||
}
|
||||
print_debug("\n*** GPIO VALUES ***\n");
|
||||
data = inb(0x68a);
|
||||
print_debug("\nGPDO 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
data = inb(0x68b);
|
||||
print_debug("\nGPDI 4: 0x");
|
||||
print_debug_hex8(data);
|
||||
print_debug("\n");
|
||||
|
||||
#if 0
|
||||
|
||||
print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
|
||||
setup_func(0x0a);
|
||||
print_reg(0xf0);
|
||||
|
||||
print_debug("\n*** FAN CONTROL REGISTERS ***\n");
|
||||
setup_func(0x09);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
|
||||
print_debug("\n*** RTC REGISTERS ***\n");
|
||||
setup_func(0x10);
|
||||
print_reg(0xf0);
|
||||
print_reg(0xf1);
|
||||
print_reg(0xf3);
|
||||
print_reg(0xf6);
|
||||
print_reg(0xf7);
|
||||
print_reg(0xfe);
|
||||
print_reg(0xff);
|
||||
|
||||
print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
|
||||
setup_func(0x14);
|
||||
print_reg(0xf0);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static void dump_bar14(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
unsigned long bar;
|
||||
|
||||
print_debug("BAR 14 Dump\n");
|
||||
|
||||
bar = pci_read_config32(dev, 0x14);
|
||||
for(i = 0; i <= 0x300; i+=4) {
|
||||
#if 0
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
#endif
|
||||
if((i%4)==0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex16(i);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug_hex32(read32(bar + i));
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void dump_spd_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = DIMM0;
|
||||
while(device <= DIMM7) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("dimm ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 256) ; i++) {
|
||||
unsigned char byte;
|
||||
if ((i % 16) == 0) {
|
||||
print_debug("\n");
|
||||
print_debug_hex8(i);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, i);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_ipmi_registers(void)
|
||||
{
|
||||
unsigned device;
|
||||
device = 0x42;
|
||||
while(device <= 0x42) {
|
||||
int status = 0;
|
||||
int i;
|
||||
print_debug("\n");
|
||||
print_debug("ipmi ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
for(i = 0; (i < 8) ; i++) {
|
||||
unsigned char byte;
|
||||
status = smbus_read_byte(device, 2);
|
||||
if (status < 0) {
|
||||
print_debug("bad device: ");
|
||||
print_debug_hex8(-status);
|
||||
print_debug("\n");
|
||||
break;
|
||||
}
|
||||
print_debug_hex8(status);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
device++;
|
||||
print_debug("\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
chip northbridge/intel/e7520 # mch
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x5580 inherit
|
||||
chip southbridge/intel/i82801ex # i82801er
|
||||
# USB ports
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.2 on end
|
||||
device pci 1d.3 on end
|
||||
device pci 1d.7 on end
|
||||
|
||||
# -> Bridge
|
||||
device pci 1e.0 on end
|
||||
|
||||
# -> ISA
|
||||
device pci 1f.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a on end
|
||||
device pnp 2e.b off end
|
||||
end
|
||||
end
|
||||
# -> IDE
|
||||
device pci 1f.1 on end
|
||||
# -> SATA
|
||||
device pci 1f.2 on end
|
||||
device pci 1f.3 on end
|
||||
|
||||
register "pirq_a_d" = "0x0b070a05"
|
||||
register "pirq_e_h" = "0x0a808080"
|
||||
end
|
||||
device pci 00.0 on end
|
||||
device pci 00.1 on end
|
||||
device pci 01.0 on end
|
||||
device pci 02.0 on
|
||||
chip southbridge/intel/pxhd # pxhd1
|
||||
# Bus bridges and ioapics usually bus 1
|
||||
device pci 0.0 on
|
||||
# On board gig e1000
|
||||
chip drivers/generic/generic
|
||||
device pci 03.0 on end
|
||||
device pci 03.1 on end
|
||||
end
|
||||
end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 0.3 on end
|
||||
end
|
||||
end
|
||||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070105"
|
||||
end
|
||||
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
0x52495024, /* u32 signature */
|
||||
0x0100, /* u16 version */
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
|
||||
0x00, /* u8 Bus 0 */
|
||||
0xf8, /* u8 Device 1, Function 0 */
|
||||
0x0000, /* u16 reserve IRQ for PCI */
|
||||
0x8086, /* u16 Vendor */
|
||||
0x24d0, /* Device ID */
|
||||
0x00000000, /* u32 miniport_data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc4, /* u8 checksum - mod 256 checksum must give zero */
|
||||
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
|
||||
{0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00},
|
||||
{0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00}
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -1,168 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_pxhd_3;
|
||||
unsigned char bus_pxhd_4;
|
||||
unsigned char bus_ich5r_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* ich5r */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
|
||||
bus_ich5r_1 = 7;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
|
||||
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
|
||||
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
|
||||
/* pxhd-3 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
|
||||
if (dev) {
|
||||
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
|
||||
|
||||
bus_pxhd_3 = 5;
|
||||
}
|
||||
/* pxhd-4 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
|
||||
if (dev) {
|
||||
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
|
||||
|
||||
bus_pxhd_4 = 6;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* pxhd apic 3 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
}
|
||||
/* pxhd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
}
|
||||
}
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x76, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x08, 0x03, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0c, 0x03, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0d, 0x03, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_2, 0x08, 0x04, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_ich5r_1, 0x04, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_4, 0x00, 0x02, 0x10);
|
||||
#if 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
(bus_isa - 1), 0x04, 0x02, 0x10);
|
||||
#endif
|
||||
/* Standard local interrupt assignments */
|
||||
#if 0
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
#endif
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801ex/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "lib/debug.c" // XXX
|
||||
#include "watchdog.c"
|
||||
#include "southbridge/intel/i82801ex/reset.c"
|
||||
#include "superio/winbond/w83627hf/early_serial.c"
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
|
||||
#define DUMMY_DEV PNP_DEV(0x2e, 0)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D0F0 | \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static void mch_reset(void) {}
|
||||
static void mainboard_set_e7520_pll(unsigned bits) {}
|
||||
static void mainboard_set_e7520_leds(void) {}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
|
||||
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
|
||||
w83627hf_set_clksel_48(DUMMY_DEV);
|
||||
w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Missing ich5?");
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
mainboard_set_e7520_leds();
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_ich5_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
static void disable_jarell_frb3(void)
|
||||
{
|
||||
#if 0
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 0);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set gpio base */
|
||||
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
|
||||
base = ICH5_GPIOBASE;
|
||||
|
||||
/* Enable GPIO Bar */
|
||||
value = pci_read_config32(dev, 0x5c);
|
||||
value |= 0x10;
|
||||
pci_write_config32(dev, 0x5c, value);
|
||||
|
||||
/* Configure GPIO 48 and 40 as GPIO */
|
||||
value = inl(base + 0x30);
|
||||
value |= (1 << 16) | ( 1 << 8);
|
||||
outl(value, base + 0x30);
|
||||
|
||||
/* Configure GPIO 48 as Output */
|
||||
value = inl(base + 0x34);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x34);
|
||||
|
||||
/* Toggle GPIO 48 high to low */
|
||||
value = inl(base + 0x38);
|
||||
value |= (1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
value &= ~(1 << 16);
|
||||
outl(value, base + 0x38);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_ich5_watchdog();
|
||||
// disable_jarell_frb3();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
|
@ -1,7 +1,5 @@
|
|||
source src/northbridge/intel/e7501/Kconfig
|
||||
source src/northbridge/intel/e7505/Kconfig
|
||||
source src/northbridge/intel/e7520/Kconfig
|
||||
source src/northbridge/intel/e7525/Kconfig
|
||||
source src/northbridge/intel/i3100/Kconfig
|
||||
source src/northbridge/intel/i440bx/Kconfig
|
||||
source src/northbridge/intel/i440lx/Kconfig
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx
|
||||
|
|
|
|||
|
|
@ -1,9 +0,0 @@
|
|||
config NORTHBRIDGE_INTEL_E7520
|
||||
bool
|
||||
|
||||
if NORTHBRIDGE_INTEL_E7520
|
||||
config DIMM_MAP_LOGICAL
|
||||
hex
|
||||
default 0x1248
|
||||
|
||||
endif
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
ramstage-y += northbridge.c
|
||||
ramstage-y += pciexp_porta.c
|
||||
ramstage-y += pciexp_porta1.c
|
||||
ramstage-y += pciexp_portb.c
|
||||
ramstage-y += pciexp_portc.c
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
struct northbridge_intel_e7520_config
|
||||
{
|
||||
/* Interrupt line connect */
|
||||
unsigned int intrline;
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#define IURBASE 0X14
|
||||
#define MCHCFG0 0X50
|
||||
#define MCHSCRB 0X52
|
||||
#define FDHC 0X58
|
||||
#define PAM 0X59
|
||||
#define DRB 0X60
|
||||
#define DRA 0X70
|
||||
#define DRT 0X78
|
||||
#define DRC 0X7C
|
||||
#define DRM 0X80
|
||||
#define DRORC 0X82
|
||||
#define ECCDIAG 0X84
|
||||
#define SDRC 0X88
|
||||
#define CKDIS 0X8C
|
||||
#define CKEDIS 0X8D
|
||||
#define DDRCSR 0X9A
|
||||
#define DEVPRES 0X9C
|
||||
#define DEVPRES_D0F0 (1 << 0)
|
||||
#define DEVPRES_D1F0 (1 << 1)
|
||||
#define DEVPRES_D2F0 (1 << 2)
|
||||
#define DEVPRES_D3F0 (1 << 3)
|
||||
#define DEVPRES_D4F0 (1 << 4)
|
||||
#define DEVPRES_D5F0 (1 << 5)
|
||||
#define DEVPRES_D6F0 (1 << 6)
|
||||
#define DEVPRES_D7F0 (1 << 7)
|
||||
#define ESMRC 0X9D
|
||||
#define SMRC 0X9E
|
||||
#define EXSMRC 0X9F
|
||||
#define DDR2ODTC 0XB0
|
||||
#define TOLM 0XC4
|
||||
#define REMAPBASE 0XC6
|
||||
#define REMAPLIMIT 0XC8
|
||||
#define REMAPOFFSET 0XCA
|
||||
#define TOM 0XCC
|
||||
#define EXPECBASE 0XCE
|
||||
#define DEVPRES1 0XF4
|
||||
#define DEVPRES1_D0F1 (1 << 5)
|
||||
#define DEVPRES1_D8F0 (1 << 1)
|
||||
#define MSCFG 0XF6
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#include "e7520.h"
|
||||
#define NB_DEV PCI_DEV(0, 0, 0)
|
||||
|
||||
static inline int memory_initialized(void)
|
||||
{
|
||||
uint32_t drc;
|
||||
drc = pci_read_config32(NB_DEV, DRC);
|
||||
//print_debug("memory_initialized: DRC: ");
|
||||
//print_debug_hex32(drc);
|
||||
//print_debug("\n");
|
||||
|
||||
return (drc & (1<<29));
|
||||
}
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include "e7520.h"
|
||||
|
||||
static unsigned int max_bus;
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
device_t mc_dev;
|
||||
uint32_t pci_tolm;
|
||||
|
||||
pci_tolm = find_pci_tolm(dev->link_list);
|
||||
|
||||
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
|
||||
|
||||
/* FIXME Me temporary hack */
|
||||
if(pci_tolm > 0xe0000000)
|
||||
pci_tolm = 0xe0000000;
|
||||
/* Ensure pci_tolm is 128M aligned */
|
||||
pci_tolm &= 0xf8000000;
|
||||
mc_dev = dev->link_list->children;
|
||||
if (mc_dev) {
|
||||
/* Figure out which areas are/should be occupied by RAM.
|
||||
* This is all computed in kilobytes and converted to/from
|
||||
* the memory controller right at the edges.
|
||||
* Having different variables in different units is
|
||||
* too confusing to get right. Kilobytes are good up to
|
||||
* 4 Terabytes of RAM...
|
||||
*/
|
||||
uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
|
||||
unsigned long tomk, tolmk;
|
||||
unsigned long remapbasek, remaplimitk, remapoffsetk;
|
||||
|
||||
/* Get the Top of Memory address, units are 128M */
|
||||
tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
|
||||
/* Compute the Top of Low Memory */
|
||||
tolmk = (pci_tolm & 0xf8000000) >> 10;
|
||||
|
||||
if (tolmk >= tomk) {
|
||||
/* The PCI hole does not overlap memory
|
||||
* we won't use the remap window.
|
||||
*/
|
||||
tolmk = tomk;
|
||||
remapbasek = 0x3ff << 16;
|
||||
remaplimitk = 0 << 16;
|
||||
remapoffsetk = 0 << 16;
|
||||
}
|
||||
else {
|
||||
/* The PCI memory hole overlaps memory
|
||||
* setup the remap window.
|
||||
*/
|
||||
/* Find the bottom of the remap window
|
||||
* is it above 4G?
|
||||
*/
|
||||
remapbasek = 4*1024*1024;
|
||||
if (tomk > remapbasek) {
|
||||
remapbasek = tomk;
|
||||
}
|
||||
/* Find the limit of the remap window */
|
||||
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
|
||||
/* Find the offset of the remap window from tolm */
|
||||
remapoffsetk = remapbasek - tolmk;
|
||||
}
|
||||
/* Write the ram configruation registers,
|
||||
* preserving the reserved bits.
|
||||
*/
|
||||
tolm_r = pci_read_config16(mc_dev, 0xc4);
|
||||
tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
|
||||
pci_write_config16(mc_dev, 0xc4, tolm_r);
|
||||
|
||||
remapbase_r = pci_read_config16(mc_dev, 0xc6);
|
||||
remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xc6, remapbase_r);
|
||||
|
||||
remaplimit_r = pci_read_config16(mc_dev, 0xc8);
|
||||
remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xc8, remaplimit_r);
|
||||
|
||||
remapoffset_r = pci_read_config16(mc_dev, 0xca);
|
||||
remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xca, remapoffset_r);
|
||||
|
||||
/* Report the memory regions */
|
||||
ram_resource(dev, 3, 0, 640);
|
||||
ram_resource(dev, 4, 768, (tolmk - 768));
|
||||
if (tomk > 4*1024*1024) {
|
||||
ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
|
||||
}
|
||||
if (remaplimitk >= remapbasek) {
|
||||
ram_resource(dev, 6, remapbasek,
|
||||
(remaplimitk + 64*1024) - remapbasek);
|
||||
}
|
||||
|
||||
set_top_of_ram(tolmk * 1024);
|
||||
}
|
||||
assign_resources(dev->link_list);
|
||||
}
|
||||
|
||||
static u32 e7520_domain_scan_bus(device_t dev, u32 max)
|
||||
{
|
||||
max_bus = pci_domain_scan_bus(dev, max);
|
||||
return max_bus;
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = e7520_domain_scan_bus,
|
||||
.ops_pci_bus = pci_bus_default_ops,
|
||||
};
|
||||
|
||||
static void mc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
resource = new_resource(dev, 0xcf);
|
||||
resource->base = 0xe0000000;
|
||||
resource->size = max_bus * 4096*256;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void mc_set_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
resource = find_resource(dev, 0xcf);
|
||||
if (resource) {
|
||||
report_resource_stored(dev, resource, "<mmconfig>");
|
||||
}
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
{
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
static struct pci_operations intel_pci_ops = {
|
||||
.set_subsystem = intel_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations mc_ops = {
|
||||
.read_resources = mc_read_resources,
|
||||
.set_resources = mc_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &intel_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver mc_driver __pci_driver = {
|
||||
.ops = &mc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x3590,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = DEVICE_NOOP,
|
||||
.set_resources = DEVICE_NOOP,
|
||||
.enable_resources = DEVICE_NOOP,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
|
||||
static void enable_dev(device_t dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_intel_e7520_ops = {
|
||||
CHIP_NAME("Intel E7520 Northbridge")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef NORTHBRIDGE_INTEL_E7520_H
|
||||
#define NORTHBRIDGE_INTEL_E7520_H
|
||||
|
||||
extern unsigned int e7520_scan_root_bus(device_t root, unsigned int max);
|
||||
|
||||
|
||||
#endif /* NORTHBRIDGE_INTEL_E7520_H */
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <reset.h>
|
||||
|
||||
typedef struct northbridge_intel_e7520_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
|
||||
{
|
||||
uint16_t val;
|
||||
uint16_t ctl;
|
||||
int flag = 0;
|
||||
do {
|
||||
val = pci_read_config16(dev, 0x76);
|
||||
printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
|
||||
if((val & (1<<10) )&&(!flag)) { /* training error */
|
||||
ctl = pci_read_config16(dev, 0x74);
|
||||
pci_write_config16(dev, 0x74, (ctl | (1<<5)));
|
||||
val = pci_read_config16(dev, 0x76);
|
||||
printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
|
||||
flag=1;
|
||||
hard_reset();
|
||||
}
|
||||
} while ( val & (3<<10) );
|
||||
return pciexp_scan_bridge(dev, max);
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pcie_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PA,
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7520_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PA1,
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7520_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PB,
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7520_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PC,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +0,0 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
unsigned node_id;
|
||||
// device_t f0, f1, f2, f3;
|
||||
u16 channel0[DIMM_SOCKETS];
|
||||
u16 channel1[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
config NORTHBRIDGE_INTEL_E7525
|
||||
bool
|
||||
|
||||
if NORTHBRIDGE_INTEL_E7525
|
||||
config DIMM_MAP_LOGICAL
|
||||
hex
|
||||
default 0x1248
|
||||
|
||||
endif
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
ramstage-y += northbridge.c
|
||||
ramstage-y += pciexp_porta.c
|
||||
ramstage-y += pciexp_porta1.c
|
||||
ramstage-y += pciexp_portb.c
|
||||
ramstage-y += pciexp_portc.c
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
struct northbridge_intel_e7525_config
|
||||
{
|
||||
/* Interrupt line connect */
|
||||
unsigned int intrline;
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#define IURBASE 0X14
|
||||
#define MCHCFG0 0X50
|
||||
#define MCHSCRB 0X52
|
||||
#define FDHC 0X58
|
||||
#define PAM 0X59
|
||||
#define DRB 0X60
|
||||
#define DRA 0X70
|
||||
#define DRT 0X78
|
||||
#define DRC 0X7C
|
||||
#define DRM 0X80
|
||||
#define DRORC 0X82
|
||||
#define ECCDIAG 0X84
|
||||
#define SDRC 0X88
|
||||
#define CKDIS 0X8C
|
||||
#define CKEDIS 0X8D
|
||||
#define DDRCSR 0X9A
|
||||
#define DEVPRES 0X9C
|
||||
#define DEVPRES_D0F0 (1 << 0)
|
||||
#define DEVPRES_D1F0 (1 << 1)
|
||||
#define DEVPRES_D2F0 (1 << 2)
|
||||
#define DEVPRES_D3F0 (1 << 3)
|
||||
#define DEVPRES_D4F0 (1 << 4)
|
||||
#define DEVPRES_D5F0 (1 << 5)
|
||||
#define DEVPRES_D6F0 (1 << 6)
|
||||
#define DEVPRES_D7F0 (1 << 7)
|
||||
#define ESMRC 0X9D
|
||||
#define SMRC 0X9E
|
||||
#define EXSMRC 0X9F
|
||||
#define DDR2ODTC 0XB0
|
||||
#define TOLM 0XC4
|
||||
#define REMAPBASE 0XC6
|
||||
#define REMAPLIMIT 0XC8
|
||||
#define REMAPOFFSET 0XCA
|
||||
#define TOM 0XCC
|
||||
#define EXPECBASE 0XCE
|
||||
#define DEVPRES1 0XF4
|
||||
#define DEVPRES1_D0F1 (1 << 5)
|
||||
#define DEVPRES1_D8F0 (1 << 1)
|
||||
#define MSCFG 0XF6
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#include "e7525.h"
|
||||
#define NB_DEV PCI_DEV(0, 0, 0)
|
||||
|
||||
static inline int memory_initialized(void)
|
||||
{
|
||||
uint32_t drc;
|
||||
drc = pci_read_config32(NB_DEV, DRC);
|
||||
return (drc & (1<<29));
|
||||
}
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include "e7525.h"
|
||||
|
||||
static unsigned int max_bus;
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
device_t mc_dev;
|
||||
uint32_t pci_tolm;
|
||||
|
||||
pci_tolm = find_pci_tolm(dev->link_list);
|
||||
|
||||
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
|
||||
/* FIXME Me temporary hack */
|
||||
if(pci_tolm > 0xe0000000)
|
||||
pci_tolm = 0xe0000000;
|
||||
/* Ensure pci_tolm is 128M aligned */
|
||||
pci_tolm &= 0xf8000000;
|
||||
mc_dev = dev->link_list->children;
|
||||
if (mc_dev) {
|
||||
/* Figure out which areas are/should be occupied by RAM.
|
||||
* This is all computed in kilobytes and converted to/from
|
||||
* the memory controller right at the edges.
|
||||
* Having different variables in different units is
|
||||
* too confusing to get right. Kilobytes are good up to
|
||||
* 4 Terabytes of RAM...
|
||||
*/
|
||||
uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
|
||||
unsigned long tomk, tolmk;
|
||||
unsigned long remapbasek, remaplimitk, remapoffsetk;
|
||||
|
||||
/* Get the Top of Memory address, units are 128M */
|
||||
tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
|
||||
/* Compute the Top of Low Memory */
|
||||
tolmk = (pci_tolm & 0xf8000000) >> 10;
|
||||
|
||||
if (tolmk >= tomk) {
|
||||
/* The PCI hole does not overlap memory
|
||||
* we won't use the remap window.
|
||||
*/
|
||||
tolmk = tomk;
|
||||
remapbasek = 0x3ff << 16;
|
||||
remaplimitk = 0 << 16;
|
||||
remapoffsetk = 0 << 16;
|
||||
}
|
||||
else {
|
||||
/* The PCI memory hole overlaps memory
|
||||
* setup the remap window.
|
||||
*/
|
||||
/* Find the bottom of the remap window
|
||||
* is it above 4G?
|
||||
*/
|
||||
remapbasek = 4*1024*1024;
|
||||
if (tomk > remapbasek) {
|
||||
remapbasek = tomk;
|
||||
}
|
||||
/* Find the limit of the remap window */
|
||||
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
|
||||
/* Find the offset of the remap window from tolm */
|
||||
remapoffsetk = remapbasek - tolmk;
|
||||
}
|
||||
/* Write the ram configruation registers,
|
||||
* preserving the reserved bits.
|
||||
*/
|
||||
tolm_r = pci_read_config16(mc_dev, 0xc4);
|
||||
tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
|
||||
pci_write_config16(mc_dev, 0xc4, tolm_r);
|
||||
|
||||
remapbase_r = pci_read_config16(mc_dev, 0xc6);
|
||||
remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xc6, remapbase_r);
|
||||
|
||||
remaplimit_r = pci_read_config16(mc_dev, 0xc8);
|
||||
remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xc8, remaplimit_r);
|
||||
|
||||
remapoffset_r = pci_read_config16(mc_dev, 0xca);
|
||||
remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
|
||||
pci_write_config16(mc_dev, 0xca, remapoffset_r);
|
||||
|
||||
/* Report the memory regions */
|
||||
ram_resource(dev, 3, 0, 640);
|
||||
ram_resource(dev, 4, 768, (tolmk - 768));
|
||||
if (tomk > 4*1024*1024) {
|
||||
ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
|
||||
}
|
||||
if (remaplimitk >= remapbasek) {
|
||||
ram_resource(dev, 6, remapbasek,
|
||||
(remaplimitk + 64*1024) - remapbasek);
|
||||
}
|
||||
|
||||
set_top_of_ram(tolmk * 1024);
|
||||
}
|
||||
assign_resources(dev->link_list);
|
||||
}
|
||||
|
||||
static u32 e7525_domain_scan_bus(device_t dev, u32 max)
|
||||
{
|
||||
max_bus = pci_domain_scan_bus(dev, max);
|
||||
return max_bus;
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = e7525_domain_scan_bus,
|
||||
.ops_pci_bus = pci_bus_default_ops,
|
||||
};
|
||||
|
||||
static void mc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
resource = new_resource(dev, 0xcf);
|
||||
resource->base = 0xe0000000;
|
||||
resource->size = max_bus * 4096*256;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void mc_set_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
resource = find_resource(dev, 0xcf);
|
||||
if (resource) {
|
||||
report_resource_stored(dev, resource, "<mmconfig>");
|
||||
}
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
{
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
static struct pci_operations intel_pci_ops = {
|
||||
.set_subsystem = intel_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations mc_ops = {
|
||||
.read_resources = mc_read_resources,
|
||||
.set_resources = mc_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &intel_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver mc_driver __pci_driver = {
|
||||
.ops = &mc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x359e,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = DEVICE_NOOP,
|
||||
.set_resources = DEVICE_NOOP,
|
||||
.enable_resources = DEVICE_NOOP,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
|
||||
static void enable_dev(device_t dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_intel_e7525_ops = {
|
||||
CHIP_NAME("Intel E7525 Northbridge")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef NORTHBRIDGE_INTEL_E7525_H
|
||||
#define NORTHBRIDGE_INTEL_E7525_H
|
||||
|
||||
extern unsigned int e7525_scan_root_bus(device_t root, unsigned int max);
|
||||
|
||||
|
||||
#endif /* NORTHBRIDGE_INTEL_E7525_H */
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7525_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PA,
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7525_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PA1,
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7525_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PB,
|
||||
};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
typedef struct northbridge_intel_e7525_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_PCIE_PC,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +0,0 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
unsigned node_id;
|
||||
device_t f0, f1, f2, f3;
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
uint16_t channel1[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
@ -10,7 +10,6 @@ source src/southbridge/intel/i82801ex/Kconfig
|
|||
source src/southbridge/intel/i82801gx/Kconfig
|
||||
source src/southbridge/intel/i82801ix/Kconfig
|
||||
source src/southbridge/intel/i82870/Kconfig
|
||||
source src/southbridge/intel/pxhd/Kconfig
|
||||
source src/southbridge/intel/sch/Kconfig
|
||||
source src/southbridge/intel/bd82x6x/Kconfig
|
||||
source src/southbridge/intel/ibexpeak/Kconfig
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex
|
|||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x
|
||||
|
|
|
|||
|
|
@ -1,2 +0,0 @@
|
|||
config SOUTHBRIDGE_INTEL_PXHD
|
||||
bool
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue