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soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition 

LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.

Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-08-14 16:30:59 +05:30 committed by Aaron Durbin
parent 07f5b62aa8
commit 588c2c42c3
1 changed files with 1 additions and 1 deletions
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src/soc/intel/cannonlake/include/soc/lpc.h
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@ -48,7 +48,7 @@
#define LGMR 0x98 /* LPC Generic Memory Range */ #define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_CNTL 0xdc #define BIOS_CNTL 0xdc
#define LPC_BC_BILD (1 << 7) /* BILD */ #define LPC_BC_BILD (1 << 7) /* BILD */
#define LPC_BC_LE (1 << 2) /* LE */ #define LPC_BC_LE (1 << 1) /* LE */
#define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_BC_EISS (1 << 5) /* EISS */
#define PCCTL 0xE0 /* PCI Clock Control */ #define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0) #define CLKRUN_EN (1 << 0)