cpu/intel/model_206ax: Use haswell cstate_map
Make the code look like on newer platforms. This doesn't change functionality. Test: Lenovo X220 still boots and advertises all C-states as before. Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78193 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -13,79 +13,52 @@
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#include "model_206ax.h"
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#include "model_206ax.h"
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#include "chip.h"
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#include "chip.h"
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#define MWAIT_RES(state, sub_state) \
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{ \
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.addrl = (((state) << 4) | (sub_state)), \
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.space_id = ACPI_ADDRESS_SPACE_FIXED, \
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
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}
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/*
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/*
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* List of supported C-states in this processor
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* List of supported C-states in this processor
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*
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*
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* Latencies are typical worst-case package exit time in uS
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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* taken from the SandyBridge BIOS specification.
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*/
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*/
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static const acpi_cstate_t cstate_map[] = {
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static acpi_cstate_t cstate_map[NUM_C_STATES] = {
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{ /* 0: C0 */
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[C_STATE_C0] = { },
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}, { /* 1: C1 */
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[C_STATE_C1] = {
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.latency = 1,
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.latency = 1,
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.power = 1000,
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.power = 1000,
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.resource = {
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.resource = MWAIT_RES(0, 0),
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.addrl = 0x00, /* MWAIT State 0 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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{ /* 2: C1E */
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[C_STATE_C1E] = {
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.latency = 1,
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.latency = 1,
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.power = 1000,
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.power = 1000,
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.resource = {
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.resource = MWAIT_RES(0, 1),
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.addrl = 0x01, /* MWAIT State 0 Sub-state 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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{ /* 3: C3 */
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[C_STATE_C3] = {
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.latency = 63,
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.latency = 63,
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.power = 500,
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.power = 500,
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.resource = {
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.resource = MWAIT_RES(1, 0),
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.addrl = 0x10, /* MWAIT State 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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{ /* 4: C6 */
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[C_STATE_C6] = {
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.latency = 87,
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.latency = 87,
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.power = 350,
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.power = 350,
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.resource = {
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.resource = MWAIT_RES(2, 0),
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.addrl = 0x20, /* MWAIT State 2 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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{ /* 5: C7 */
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[C_STATE_C7] = {
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.latency = 90,
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.latency = 90,
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.power = 200,
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.power = 200,
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.resource = {
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.resource = MWAIT_RES(3, 0),
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.addrl = 0x30, /* MWAIT State 3 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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{ /* 6: C7S */
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[C_STATE_C7S] = {
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.latency = 90,
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.latency = 90,
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.power = 200,
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.power = 200,
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.resource = {
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.resource = MWAIT_RES(3, 1),
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.addrl = 0x31, /* MWAIT State 3 Sub-state 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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},
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};
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};
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@ -109,6 +109,20 @@
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# error "CONFIG_IED_REGION_SIZE is not a power of 2"
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# error "CONFIG_IED_REGION_SIZE is not a power of 2"
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#endif
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#endif
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/*
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* List of supported C-states for Sandy Bridge/Ivy Bridge.
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*/
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enum {
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C_STATE_C0 = 0,
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C_STATE_C1 = 1,
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C_STATE_C1E = 2,
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C_STATE_C3 = 3,
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C_STATE_C6 = 4,
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C_STATE_C7 = 5,
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C_STATE_C7S = 6,
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NUM_C_STATES,
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};
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/* Lock MSRs */
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/* Lock MSRs */
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void intel_model_206ax_finalize_smm(void);
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void intel_model_206ax_finalize_smm(void);
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