nb/intel/sandybridge/raminit: fix regression "always use mrccache"
Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -4038,7 +4038,7 @@ static void restore_timings(ramctr_timing * ctrl)
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}
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static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
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int me_uma_size)
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int s3_resume, int me_uma_size)
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{
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int err;
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@ -4148,9 +4148,11 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
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write_controller_mr(ctrl);
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if (!s3_resume) {
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err = channel_test(ctrl);
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if (err)
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return err;
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}
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return 0;
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}
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@ -4228,9 +4230,14 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
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printk(BIOS_DEBUG, "Trying stored timings.\n");
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memcpy(&ctrl, ctrl_cached, sizeof(ctrl));
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err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
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err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
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if (err) {
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/* no need to erase bad mrc cache here, it gets overritten on
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if (s3resume) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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halt();
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}
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/* no need to erase bad mrc cache here, it gets overwritten on
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* successful boot. */
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printk(BIOS_ERR, "Stored timings are invalid !\n");
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fast_boot = 0;
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@ -4243,7 +4250,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
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/* Get DDR3 SPD data */
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dram_find_spds_ddr3(spds, &ctrl);
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err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
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err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
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}
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if (err)
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die("raminit failed");
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