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mb/intel/mtlrvp: Describe TCSS USB ports 

This patch describes the TCSS USB ports for mtlrvp as per schematics.
This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below,
tcss_usb3_port1: USB3 Type-C Port C0
tcss_usb3_port2: USB3 Type-C Port C1
tcss_usb3_port3: USB3 Type-C Port C2
tcss_usb3_port4: USB3 Type-C Port C3

BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration
of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C
ports as part of cbmem -c.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Harsha B R 2023-02-04 12:56:01 +05:30 committed by Sridhar Siricilla
parent 4aa7d2d5ac
commit 5897382269
1 changed files with 30 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -91,7 +91,36 @@ chip soc/intel/meteorlake
device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end device ref tbt_pcie_rp3 on end
device ref tcss_xhci on end device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(4, 2)"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 2)"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref tcss_usb3_port4 on end
end
end
end
end
device ref tcss_dma0 on end device ref tcss_dma0 on end
device ref tcss_dma1 on end device ref tcss_dma1 on end
device ref pcie_rp7 on device ref pcie_rp7 on
@ -144,7 +173,6 @@ chip soc/intel/meteorlake
}" }"
end # PCIE11 SSD Gen4 end # PCIE11 SSD Gen4
device ref xhci on end device ref xhci on end
device ref cnvi_wifi on device ref cnvi_wifi on
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
@ -152,7 +180,6 @@ chip soc/intel/meteorlake
device generic 0 on end device generic 0 on end
end end
end end
device ref i2c0 on end device ref i2c0 on end
device ref i2c1 on end device ref i2c1 on end
device ref i2c2 on end device ref i2c2 on end