- Small step forward Linux boots and almost works...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
8ca8d7665d
commit
5899fd82aa
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@ -18,6 +18,7 @@
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#define APIC 1
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#endif
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static void cache_on(struct mem_range *mem)
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{
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post_code(0x60);
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@ -90,6 +91,11 @@ static void interrupts_on()
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| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING |
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APIC_DELIVERY_MODE_NMI)
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);
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#if 1
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printk_debug(" apic_id: %d ",
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apic_read(APIC_ID));
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#endif
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#else /* APIC */
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#ifdef i686
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/* Only Pentium Pro and later have those MSR stuff */
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@ -1,9 +1,9 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/pciconf.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <pci_ops.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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static const struct pci_ops *conf;
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struct pci_ops {
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@ -0,0 +1,86 @@
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#include <console/console.h>
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#include <arch/ioapic.h>
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/* TODO: this must move to chip/intel */
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/* we have to do more than we thought. I assumed Linux would do all the
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* interesting parts, and I was wrong.
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*/
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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};
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struct ioapicreg ioapicregvalues[] = {
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#define ALL (0xff << 24)
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#define NONE (0)
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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/* mask, trigger, polarity, destination, delivery, vector */
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{0x00, DISABLED, NONE},
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{0x01, DISABLED, NONE},
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{0x02, DISABLED, NONE},
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{0x03, DISABLED, NONE},
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{0x04, DISABLED, NONE},
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{0x05, DISABLED, NONE},
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{0x06, DISABLED, NONE},
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{0x07, DISABLED, NONE},
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{0x08, DISABLED, NONE},
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{0x09, DISABLED, NONE},
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{0x0a, DISABLED, NONE},
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{0x0b, DISABLED, NONE},
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{0x0c, DISABLED, NONE},
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{0x0d, DISABLED, NONE},
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{0x0e, DISABLED, NONE},
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{0x0f, DISABLED, NONE},
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{0x10, DISABLED, NONE},
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{0x11, DISABLED, NONE},
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{0x12, DISABLED, NONE},
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{0x13, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x15, DISABLED, NONE},
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{0x16, DISABLED, NONE},
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{0x17, DISABLED, NONE},
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};
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void setup_ioapic(void)
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{
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int i;
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unsigned long value_low, value_high;
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unsigned long nvram = 0xfec00000;
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volatile unsigned long *l;
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struct ioapicreg *a = ioapicregvalues;
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l = (unsigned long *) nvram;
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#if defined(i786)
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/* For the pentium 4 and above apic deliver their interrupts
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* on the front side bus, enable that.
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*/
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l[0] = 0x03;
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l[4] = 1;
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#endif /* i786 */
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for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
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i++, a++) {
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l[0] = (a->reg * 2) + 0x10;
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l[4] = a->value_low;
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value_low = l[4];
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l[0] = (a->reg *2) + 0x11;
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l[4] = a->value_high;
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value_high = l[4];
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if ((i==0) && (value_low == 0xffffffff)) {
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printk_warning("IO APIC not responding.\n");
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return;
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}
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printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
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a->reg, a->value_low, a->value_high);
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}
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}
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@ -113,14 +113,13 @@ void smp_write_processors(struct mp_config_table *mc,
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unsigned long cpu_flag;
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if(initial_apicid[i]==-1)
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continue;
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cpu_flag = MPC_CPU_ENABLED
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cpu_flag = MPC_CPU_ENABLED;
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if (processor_map[i] & CPU_BOOTPROCESSOR) {
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cpu_flag |= MPC_CPU_BOOTPROCESSOR;
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}
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smp_write_processor(mc, cpu_apicid, apic_version,
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cpu_flag, cpu_features, cpu_feature_flags
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);
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}
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}
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@ -0,0 +1,249 @@
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#include <smp/start_stop.h>
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#include <arch/smp/mpspec.h>
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#include <cpu/p6/apic.h>
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#include <delay.h>
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#include <string.h>
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#ifndef START_CPU_SEG
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#define START_CPU_SEG 0x90000
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#endif
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#if (START_CPU_SEG&0xffff) != 0
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#error START_CPU_SEG must be 64k aligned
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#endif
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static inline void hlt(void)
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{
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asm("hlt");
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return;
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}
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unsigned long this_processors_id(void)
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{
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return apic_read(APIC_ID) >> 24;
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}
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int processor_index(unsigned long apicid)
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{
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int i;
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for(i = 0; i < MAX_CPUS; i++) {
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if (initial_apicid[i] == apicid) {
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return i;
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}
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}
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return -1;
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}
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void stop_cpu(unsigned long apicid)
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{
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int timeout;
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unsigned long send_status;
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/* send an APIC INIT to myself */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* wait for the ipi send to finish */
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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printk_spew("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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if (timeout >= 1000) {
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printk_err("timed out\n");
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}
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mdelay(10);
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printk_spew("Deasserting INIT.\n");
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/* Deassert the APIC INIT */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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printk_spew("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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if (timeout >= 1000) {
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printk_err("timed out\n");
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}
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while(1) {
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hlt();
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}
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}
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/* This is a lot more paranoid now, since Linux can NOT handle
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* being told there is a CPU when none exists. So any errors
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* will return 0, meaning no CPU.
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*
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* We actually handling that case by noting which cpus startup
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* and not telling anyone about the ones that dont.
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*/
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int start_cpu(unsigned long apicid)
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{
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int timeout;
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unsigned long send_status, accept_status, start_eip;
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int j, num_starts, maxlvt;
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extern char _secondary_start[];
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/*
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* Starting actual IPI sequence...
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*/
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printk_spew("Asserting INIT.\n");
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/*
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* Turn INIT on target chip
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*/
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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/*
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* Send IPI
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*/
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
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| APIC_DM_INIT);
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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printk_spew("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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if (timeout >= 1000) {
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printk_err("CPU %d: First apic write timed out. Disabling\n",
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apicid);
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// too bad.
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printk_err("ESR is 0x%x\n", apic_read(APIC_ESR));
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if (apic_read(APIC_ESR)) {
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printk_err("Try to reset ESR\n");
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apic_write_around(APIC_ESR, 0);
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printk_err("ESR is 0x%x\n", apic_read(APIC_ESR));
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}
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return 0;
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}
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mdelay(10);
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printk_spew("Deasserting INIT.\n");
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/* Target chip */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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/* Send IPI */
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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printk_spew("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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if (timeout >= 1000) {
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printk_err("CPU %d: Second apic write timed out. Disabling\n",
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apicid);
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// too bad.
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return 0;
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}
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start_eip = (unsigned long)_secondary_start;
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printk_spew("start_eip=0x%08lx\n", start_eip);
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num_starts = 2;
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/*
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* Run STARTUP IPI loop.
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*/
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printk_spew("#startup loops: %d.\n", num_starts);
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maxlvt = 4;
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for (j = 1; j <= num_starts; j++) {
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printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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printk_spew("After apic_write.\n");
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/*
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* STARTUP IPI
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*/
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/* Target chip */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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/* Boot on the stack */
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/* Kick the second */
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apic_write_around(APIC_ICR, APIC_DM_STARTUP
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| (start_eip >> 12));
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/*
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* Give the other CPU some time to accept the IPI.
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*/
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udelay(300);
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printk_spew("Startup point 1.\n");
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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printk_spew("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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/*
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* Give the other CPU some time to accept the IPI.
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*/
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udelay(200);
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/*
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* Due to the Pentium erratum 3AP.
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*/
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if (maxlvt > 3) {
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
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}
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accept_status = (apic_read(APIC_ESR) & 0xEF);
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if (send_status || accept_status)
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break;
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}
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printk_spew("After Startup.\n");
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if (send_status)
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printk_warning("APIC never delivered???\n");
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if (accept_status)
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printk_warning("APIC delivery error (%lx).\n", accept_status);
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if (send_status || accept_status)
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return 0;
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return 1;
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}
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void startup_other_cpus(unsigned long *processor_map)
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{
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unsigned long apicid = this_processors_id();
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int i;
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/* Assume the cpus are densly packed by apicid */
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for(i = 0; i < MAX_CPUS; i++) {
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unsigned long cpu_apicid = initial_apicid[i];
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if (cpu_apicid == -1) {
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printk_err("CPU %d not found\n",i);
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processor_map[i] = 0;
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continue;
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}
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if (cpu_apicid == apicid ) {
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continue;
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}
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if (!start_cpu(cpu_apicid)) {
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/* Put an error in processor_map[i]? */
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printk_err("CPU %d/%u would not start!\n",
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i, cpu_apicid);
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processor_map[i] = 0;
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}
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}
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}
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@ -33,8 +33,8 @@ it with the version available from LANL.
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#include <smp/start_stop.h>
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#include <boot/tables.h>
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#include <part/sizeram.h>
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#include <device.h>
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#include <pci.h>
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#include <device/device.h>
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#include <device/pci.h>
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#if 0
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#include <part/mainboard.h>
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#endif
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@ -49,7 +49,7 @@ SECTIONS
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econsole_drivers = . ;
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. = ALIGN(4);
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pci_drivers = . ;
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*(.rodata.pci_drivers)
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*(.rodata.pci_driver)
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epci_drivers = . ;
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*(.rodata)
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*(.rodata.*)
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@ -15,9 +15,9 @@
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#include <console/console.h>
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#include <bitops.h>
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#include <device.h>
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#include <arch/io.h>
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#include <pci.h>
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#include <device/device.h>
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#include <device/pci.h>
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/**
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* This is the root of the device tree. A PCI tree always has
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|
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@ -1,5 +1,5 @@
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#include <console/console.h>
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#include <device.h>
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#include <device/device.h>
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/**
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* Given a bus and a devfn number, find the device structure
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|
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@ -13,9 +13,10 @@
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#include <stdlib.h>
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#include <stdint.h>
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#include <bitops.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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static unsigned int pci_scan_bridge(struct device *bus, unsigned int max);
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@ -219,7 +220,7 @@ static void pci_bridge_read_bases(struct device *dev)
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}
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static void pci_dev_read_resources(struct device *dev)
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void pci_dev_read_resources(struct device *dev)
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{
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uint32_t addr;
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dev->resources = 0;
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@ -229,7 +230,7 @@ static void pci_dev_read_resources(struct device *dev)
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dev->rom_address = (addr == 0xffffffff)? 0 : addr;
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}
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static void pci_bus_read_resources(struct device *dev)
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void pci_bus_read_resources(struct device *dev)
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{
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uint32_t addr;
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dev->resources = 0;
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@ -345,7 +346,7 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
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return;
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}
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static void pci_dev_set_resources(struct device *dev)
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void pci_dev_set_resources(struct device *dev)
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{
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struct resource *resource, *last;
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uint8_t line;
|
||||
|
|
@ -399,9 +400,16 @@ static void set_pci_ops(struct device *dev)
|
|||
*/
|
||||
for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
|
||||
if ((driver->vendor == dev->vendor) &&
|
||||
(driver->device = dev->device)) {
|
||||
(driver->device == dev->device)) {
|
||||
dev->ops = driver->ops;
|
||||
break;
|
||||
#if 1
|
||||
printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] ops\n",
|
||||
dev->bus->secondary,
|
||||
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
|
||||
driver->vendor, driver->device
|
||||
);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
}
|
||||
/* If I don't have a specific driver use the default operations */
|
||||
|
|
@ -450,6 +458,7 @@ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
|
|||
}
|
||||
|
||||
|
||||
#define HYPERTRANSPORT_SUPPORT 1
|
||||
/** Scan the pci bus devices and bridges.
|
||||
* @param pci_bus pointer to the bus structure
|
||||
* @param max current bus number
|
||||
|
|
@ -461,6 +470,9 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
|
|||
struct device *dev, **bus_last;
|
||||
struct device *old_devices;
|
||||
struct device *child;
|
||||
#if HYPERTRANSPORT_SUPPORT
|
||||
unsigned next_unitid, last_unitid;
|
||||
#endif
|
||||
|
||||
printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
|
||||
|
||||
|
|
@ -471,6 +483,58 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
|
|||
post_code(0x24);
|
||||
|
||||
|
||||
#if HYPERTRANSPORT_SUPPORT
|
||||
/* If present assign unitid to a hypertransport chain */
|
||||
next_unitid = 1;
|
||||
do {
|
||||
struct device dummy;
|
||||
uint32_t id;
|
||||
uint8_t hdr_type, pos;
|
||||
last_unitid = next_unitid;
|
||||
|
||||
dummy.bus = bus;
|
||||
dummy.devfn = 0;
|
||||
pci_read_config_dword(&dummy, PCI_VENDOR_ID, &id);
|
||||
if (id == 0xffffffff || id == 0x00000000 ||
|
||||
id == 0x0000ffff || id == 0xffff0000) {
|
||||
break;
|
||||
}
|
||||
pci_read_config_byte(&dummy, PCI_HEADER_TYPE, &hdr_type);
|
||||
pos = 0;
|
||||
switch(hdr_type & 0x7f) {
|
||||
case PCI_HEADER_TYPE_NORMAL:
|
||||
case PCI_HEADER_TYPE_BRIDGE:
|
||||
pos = PCI_CAPABILITY_LIST;
|
||||
break;
|
||||
}
|
||||
if (pos > PCI_CAP_LIST_NEXT) {
|
||||
pci_read_config_byte(&dummy, pos, &pos);
|
||||
}
|
||||
while(pos != 0) {
|
||||
uint8_t cap;
|
||||
pci_read_config_byte(&dummy, pos + PCI_CAP_LIST_ID, &cap);
|
||||
printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
|
||||
if (cap == PCI_CAP_ID_HT) {
|
||||
uint16_t flags;
|
||||
pci_read_config_word(&dummy, pos + PCI_CAP_FLAGS, &flags);
|
||||
printk_debug("flags: 0x%04x\n", (unsigned)flags);
|
||||
if ((flags >> 13) == 0) {
|
||||
unsigned count;
|
||||
flags &= ~0x1f;
|
||||
flags |= next_unitid & 0x1f;
|
||||
count = (flags >> 5) & 0x1f;
|
||||
printk_debug("unitid: 0x%02x, count: 0x%02x\n",
|
||||
next_unitid, count);
|
||||
pci_write_config_word(&dummy, pos + PCI_CAP_FLAGS, flags);
|
||||
next_unitid += count;
|
||||
break;
|
||||
}
|
||||
}
|
||||
pci_read_config_byte(&dummy, pos + PCI_CAP_LIST_NEXT, &pos);
|
||||
}
|
||||
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
|
||||
#endif /* HYPERTRANSPORT_SUPPORT */
|
||||
|
||||
/* probe all devices on this bus with some optimization for non-existance and
|
||||
single funcion devices */
|
||||
for (devfn = 0; devfn < 0xff; devfn++) {
|
||||
|
|
@ -575,7 +639,7 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
|
|||
* @param pci_bus pointer to the bus structure
|
||||
* @return The maximum bus number found, after scanning all subordinate busses
|
||||
*/
|
||||
static unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
|
||||
unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
|
||||
{
|
||||
uint32_t buses;
|
||||
uint16_t cr;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,91 @@
|
|||
#ifndef DEVICE_H
|
||||
#define DEVICE_H
|
||||
|
||||
#include <device/resource.h>
|
||||
|
||||
struct device;
|
||||
struct device_operations {
|
||||
void (*read_resources)(struct device *dev);
|
||||
void (*set_resources)(struct device *dev);
|
||||
void (*init)(struct device *dev);
|
||||
unsigned int (*scan_bus)(struct device *bus, unsigned int max);
|
||||
};
|
||||
|
||||
|
||||
#define MAX_RESOURCES 6
|
||||
/*
|
||||
* There is one pci_dev structure for each slot-number/function-number
|
||||
* combination:
|
||||
*/
|
||||
|
||||
struct device {
|
||||
struct device *bus; /* bus this device is on */
|
||||
struct device *children; /* devices behind this bridge */
|
||||
struct device *sibling; /* next device on this bus */
|
||||
struct device *next; /* chain of all devices */
|
||||
|
||||
unsigned int devfn; /* encoded device & function index */
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
|
||||
unsigned int hdr_type; /* PCI header type */
|
||||
unsigned int master : 1; /* set if device is master capable */
|
||||
|
||||
unsigned char secondary; /* secondary bus number */
|
||||
unsigned char subordinate; /* max subordinate bus number */
|
||||
uint8_t command;
|
||||
/*
|
||||
* In theory, the irq level can be read from configuration
|
||||
* space and all would be fine. However, old PCI chips don't
|
||||
* support these registers and return 0 instead. For example,
|
||||
* the Vision864-P rev 0 chip can uses INTA, but returns 0 in
|
||||
* the interrupt line and pin registers. pci_init()
|
||||
* initializes this field with the value at PCI_INTERRUPT_LINE
|
||||
* and it is the job of pcibios_fixup() to change it if
|
||||
* necessary. The field must not be 0 unless the device
|
||||
* cannot generate interrupts at all.
|
||||
*/
|
||||
unsigned int irq; /* irq generated by this device */
|
||||
|
||||
/* Base registers for this device, can be adjusted by
|
||||
* pcibios_fixup() as necessary.
|
||||
*/
|
||||
struct resource resource[MAX_RESOURCES];
|
||||
unsigned int resources;
|
||||
unsigned long rom_address;
|
||||
struct device_operations *ops;
|
||||
|
||||
};
|
||||
|
||||
extern struct device dev_root; /* root bus */
|
||||
extern struct device *all_devices; /* list of all devices */
|
||||
|
||||
|
||||
/* Generic device interface functions */
|
||||
extern void dev_enumerate(void);
|
||||
extern void dev_configure(void);
|
||||
extern void dev_enable(void);
|
||||
extern void dev_initialize(void);
|
||||
|
||||
/* Generic device helper functions */
|
||||
void append_device(struct device *dev);
|
||||
void compute_allocate_resource(struct device *bus, struct resource *bridge,
|
||||
unsigned long type_mask, unsigned long type);
|
||||
void assign_resources(struct device *bus);
|
||||
void enumerate_static_device(void);
|
||||
unsigned long device_memory_base;
|
||||
|
||||
|
||||
/* Helper functions */
|
||||
struct device *dev_find_device (unsigned int vendor, unsigned int device, struct device *from);
|
||||
struct device *dev_find_class (unsigned int class, struct device *from);
|
||||
struct device *dev_find_slot (unsigned int bus, unsigned int devfn);
|
||||
|
||||
/* Rounding for boundaries.
|
||||
* Due to some chip bugs, go ahead and roung IO to 16
|
||||
*/
|
||||
#define DEVICE_IO_ALIGN 16
|
||||
#define DEVICE_MEM_ALIGN 4096
|
||||
|
||||
|
||||
#endif /* DEVICE_H */
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
/*
|
||||
* $Id$
|
||||
*
|
||||
* PCI defines and function prototypes
|
||||
* Copyright 1994, Drew Eckhardt
|
||||
* Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
|
||||
*
|
||||
* For more information, please consult the following manuals (look at
|
||||
* http://www.pcisig.com/ for how to get them):
|
||||
*
|
||||
* PCI BIOS Specification
|
||||
* PCI Local Bus Specification
|
||||
* PCI to PCI Bridge Specification
|
||||
* PCI System Design Guide
|
||||
*/
|
||||
|
||||
#ifndef PCI_H
|
||||
#define PCI_H
|
||||
|
||||
/*
|
||||
* Under PCI, each device has 256 bytes of configuration address space,
|
||||
* of which the first 64 bytes are standardized as follows:
|
||||
*/
|
||||
#define PCI_VENDOR_ID 0x00 /* 16 bits */
|
||||
#define PCI_DEVICE_ID 0x02 /* 16 bits */
|
||||
#define PCI_COMMAND 0x04 /* 16 bits */
|
||||
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
|
||||
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
|
||||
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
|
||||
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
|
||||
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
|
||||
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
|
||||
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
|
||||
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
|
||||
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
|
||||
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
|
||||
|
||||
#define PCI_STATUS 0x06 /* 16 bits */
|
||||
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
|
||||
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
|
||||
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
|
||||
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
|
||||
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
|
||||
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
|
||||
#define PCI_STATUS_DEVSEL_FAST 0x000
|
||||
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
|
||||
#define PCI_STATUS_DEVSEL_SLOW 0x400
|
||||
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
|
||||
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
|
||||
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
|
||||
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
|
||||
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
|
||||
|
||||
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
|
||||
revision */
|
||||
#define PCI_REVISION_ID 0x08 /* Revision ID */
|
||||
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
|
||||
#define PCI_CLASS_DEVICE 0x0a /* Device class */
|
||||
|
||||
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
|
||||
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
|
||||
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
|
||||
#define PCI_HEADER_TYPE_NORMAL 0
|
||||
#define PCI_HEADER_TYPE_BRIDGE 1
|
||||
#define PCI_HEADER_TYPE_CARDBUS 2
|
||||
|
||||
#define PCI_BIST 0x0f /* 8 bits */
|
||||
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
|
||||
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
|
||||
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
|
||||
|
||||
/*
|
||||
* Base addresses specify locations in memory or I/O space.
|
||||
* Decoded size can be determined by writing a value of
|
||||
* 0xffffffff to the register, and reading it back. Only
|
||||
* 1 bits are decoded.
|
||||
*/
|
||||
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
|
||||
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
|
||||
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
|
||||
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
|
||||
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
|
||||
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
|
||||
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
|
||||
/* bit 1 is reserved if address_space = 1 */
|
||||
|
||||
/* Header type 0 (normal devices) */
|
||||
#define PCI_CARDBUS_CIS 0x28
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
|
||||
#define PCI_SUBSYSTEM_ID 0x2e
|
||||
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
|
||||
#define PCI_ROM_ADDRESS_ENABLE 0x01
|
||||
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
|
||||
|
||||
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
|
||||
|
||||
/* 0x35-0x3b are reserved */
|
||||
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
|
||||
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
|
||||
#define PCI_MIN_GNT 0x3e /* 8 bits */
|
||||
#define PCI_MAX_LAT 0x3f /* 8 bits */
|
||||
|
||||
/* Header type 1 (PCI-to-PCI bridges) */
|
||||
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
|
||||
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
|
||||
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
|
||||
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
|
||||
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
|
||||
#define PCI_IO_LIMIT 0x1d
|
||||
#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
|
||||
#define PCI_IO_RANGE_TYPE_16 0x00
|
||||
#define PCI_IO_RANGE_TYPE_32 0x01
|
||||
#define PCI_IO_RANGE_MASK ~0x0f
|
||||
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
|
||||
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
|
||||
#define PCI_MEMORY_LIMIT 0x22
|
||||
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
|
||||
#define PCI_MEMORY_RANGE_MASK ~0x0f
|
||||
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
|
||||
#define PCI_PREF_MEMORY_LIMIT 0x26
|
||||
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
|
||||
#define PCI_PREF_RANGE_TYPE_32 0x00
|
||||
#define PCI_PREF_RANGE_TYPE_64 0x01
|
||||
#define PCI_PREF_RANGE_MASK ~0x0f
|
||||
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
|
||||
#define PCI_PREF_LIMIT_UPPER32 0x2c
|
||||
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
|
||||
#define PCI_IO_LIMIT_UPPER16 0x32
|
||||
/* 0x34 same as for htype 0 */
|
||||
/* 0x35-0x3b is reserved */
|
||||
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
|
||||
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
|
||||
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
|
||||
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
|
||||
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
|
||||
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
|
||||
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
|
||||
|
||||
/* Header type 2 (CardBus bridges) */
|
||||
#define PCI_CB_CAPABILITY_LIST 0x14
|
||||
/* 0x15 reserved */
|
||||
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
|
||||
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
|
||||
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
|
||||
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
|
||||
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
|
||||
#define PCI_CB_MEMORY_BASE_0 0x1c
|
||||
#define PCI_CB_MEMORY_LIMIT_0 0x20
|
||||
#define PCI_CB_MEMORY_BASE_1 0x24
|
||||
#define PCI_CB_MEMORY_LIMIT_1 0x28
|
||||
#define PCI_CB_IO_BASE_0 0x2c
|
||||
#define PCI_CB_IO_BASE_0_HI 0x2e
|
||||
#define PCI_CB_IO_LIMIT_0 0x30
|
||||
#define PCI_CB_IO_LIMIT_0_HI 0x32
|
||||
#define PCI_CB_IO_BASE_1 0x34
|
||||
#define PCI_CB_IO_BASE_1_HI 0x36
|
||||
#define PCI_CB_IO_LIMIT_1 0x38
|
||||
#define PCI_CB_IO_LIMIT_1_HI 0x3a
|
||||
#define PCI_CB_IO_RANGE_MASK ~0x03
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_CB_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
|
||||
#define PCI_CB_BRIDGE_CTL_SERR 0x02
|
||||
#define PCI_CB_BRIDGE_CTL_ISA 0x04
|
||||
#define PCI_CB_BRIDGE_CTL_VGA 0x08
|
||||
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
|
||||
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
|
||||
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
|
||||
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
|
||||
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
|
||||
#define PCI_CB_SUBSYSTEM_ID 0x42
|
||||
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
|
||||
/* 0x48-0x7f reserved */
|
||||
|
||||
/* Capability lists */
|
||||
|
||||
#define PCI_CAP_LIST_ID 0 /* Capability ID */
|
||||
#define PCI_CAP_ID_PM 0x01 /* Power Management */
|
||||
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
|
||||
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
|
||||
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
|
||||
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
|
||||
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
|
||||
#define PCI_CAP_ID_HT 0x08
|
||||
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
|
||||
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
|
||||
#define PCI_CAP_SIZEOF 4
|
||||
|
||||
/* Power Management Registers */
|
||||
|
||||
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
|
||||
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
|
||||
#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
|
||||
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
|
||||
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
|
||||
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
|
||||
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
|
||||
#define PCI_PM_CTRL 4 /* PM control and status register */
|
||||
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
|
||||
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
|
||||
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
||||
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
||||
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
||||
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
|
||||
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
|
||||
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
|
||||
#define PCI_PM_DATA_REGISTER 7 /* (??) */
|
||||
#define PCI_PM_SIZEOF 8
|
||||
|
||||
/* AGP registers */
|
||||
|
||||
#define PCI_AGP_VERSION 2 /* BCD version number */
|
||||
#define PCI_AGP_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_AGP_STATUS 4 /* Status register */
|
||||
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
|
||||
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
|
||||
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
|
||||
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
|
||||
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
|
||||
#define PCI_AGP_COMMAND 8 /* Control register */
|
||||
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
|
||||
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
|
||||
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
|
||||
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
|
||||
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
|
||||
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
|
||||
#define PCI_AGP_SIZEOF 12
|
||||
|
||||
/* Slot Identification */
|
||||
|
||||
#define PCI_SID_ESR 2 /* Expansion Slot Register */
|
||||
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
|
||||
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
|
||||
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
|
||||
|
||||
/* Message Signalled Interrupts registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Various flags */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
|
||||
#define PCI_MSI_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
|
||||
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
||||
|
||||
/*
|
||||
* The PCI interface treats multi-function devices as independent
|
||||
* devices. The slot/function address of each device is encoded
|
||||
* in a single byte as follows:
|
||||
*
|
||||
* 7:3 = slot
|
||||
* 2:0 = function
|
||||
*/
|
||||
#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
|
||||
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
|
||||
#define PCI_FUNC(devfn) ((devfn) & 0x07)
|
||||
#define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8)
|
||||
|
||||
|
||||
#include <device/resource.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
|
||||
struct pci_driver {
|
||||
struct device_operations *ops;
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
};
|
||||
|
||||
#define __pci_driver __attribute__ ((unused,__section__(".rodata.pci_driver")))
|
||||
extern struct pci_driver pci_drivers[];
|
||||
extern struct pci_driver epci_drivers[];
|
||||
|
||||
|
||||
struct device_operations default_pci_ops_dev;
|
||||
struct device_operations default_pci_ops_bus;
|
||||
struct device_operations default_pci_ops_root;
|
||||
|
||||
|
||||
void pci_dev_read_resources(struct device *dev);
|
||||
void pci_bus_read_resources(struct device *dev);
|
||||
void pci_dev_set_resources(struct device *dev);
|
||||
unsigned int pci_scan_bridge(struct device *bus, unsigned int max);
|
||||
|
||||
#define PCI_IO_BRIDGE_ALIGN 4096
|
||||
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
|
||||
|
||||
#endif /* PCI_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,15 @@
|
|||
#ifndef PCI_OPS_H
|
||||
#define PCI_OPS_H
|
||||
|
||||
#include <stdint.h>
|
||||
struct device;
|
||||
|
||||
int pci_read_config_byte(struct device *dev, uint8_t where, uint8_t *val);
|
||||
int pci_read_config_word(struct device *dev, uint8_t where, uint16_t *val);
|
||||
int pci_read_config_dword(struct device *dev, uint8_t where, uint32_t *val);
|
||||
int pci_write_config_byte(struct device *dev, uint8_t where, uint8_t val);
|
||||
int pci_write_config_word(struct device *dev, uint8_t where, uint16_t val);
|
||||
int pci_write_config_dword(struct device *dev, uint8_t where, uint32_t val);
|
||||
void pci_set_method(void);
|
||||
|
||||
#endif /* PCI_OPS_H */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
#ifndef RESOURCE_H
|
||||
#define RESOURCE_H
|
||||
|
||||
|
||||
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */
|
||||
|
||||
#define IORESOURCE_IO 0x00000100 /* Resource type */
|
||||
#define IORESOURCE_MEM 0x00000200
|
||||
#define IORESOURCE_IRQ 0x00000400
|
||||
#define IORESOURCE_DMA 0x00000800
|
||||
|
||||
#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
|
||||
#define IORESOURCE_READONLY 0x00002000
|
||||
#define IORESOURCE_CACHEABLE 0x00004000
|
||||
#define IORESOURCE_RANGELENGTH 0x00008000
|
||||
#define IORESOURCE_SHADOWABLE 0x00010000
|
||||
#define IORESOURCE_BUS_HAS_VGA 0x00020000
|
||||
|
||||
#define IORESOURCE_SET 0x80000000
|
||||
|
||||
/* PCI specific resource bits */
|
||||
#define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */
|
||||
#define IORESOURCE_PCI_BRIDGE (1<<1) /* A bridge pci resource */
|
||||
|
||||
/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
|
||||
#define IORESOURCE_IRQ_HIGHEDGE (1<<0)
|
||||
#define IORESOURCE_IRQ_LOWEDGE (1<<1)
|
||||
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
|
||||
#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
|
||||
|
||||
/* ISA PnP DMA specific bits (IORESOURCE_BITS) */
|
||||
#define IORESOURCE_DMA_TYPE_MASK (3<<0)
|
||||
#define IORESOURCE_DMA_8BIT (0<<0)
|
||||
#define IORESOURCE_DMA_8AND16BIT (1<<0)
|
||||
#define IORESOURCE_DMA_16BIT (2<<0)
|
||||
|
||||
#define IORESOURCE_DMA_MASTER (1<<2)
|
||||
#define IORESOURCE_DMA_BYTE (1<<3)
|
||||
#define IORESOURCE_DMA_WORD (1<<4)
|
||||
|
||||
#define IORESOURCE_DMA_SPEED_MASK (3<<6)
|
||||
#define IORESOURCE_DMA_COMPATIBLE (0<<6)
|
||||
#define IORESOURCE_DMA_TYPEA (1<<6)
|
||||
#define IORESOURCE_DMA_TYPEB (2<<6)
|
||||
#define IORESOURCE_DMA_TYPEF (3<<6)
|
||||
|
||||
|
||||
/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
|
||||
#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */
|
||||
#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */
|
||||
#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */
|
||||
#define IORESOURCE_MEM_TYPE_MASK (3<<3)
|
||||
#define IORESOURCE_MEM_8BIT (0<<3)
|
||||
#define IORESOURCE_MEM_16BIT (1<<3)
|
||||
#define IORESOURCE_MEM_8AND16BIT (2<<3)
|
||||
#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */
|
||||
#define IORESOURCE_MEM_EXPANSIONROM (1<<6)
|
||||
|
||||
struct resource {
|
||||
unsigned long base; /* Base address of the resource */
|
||||
unsigned long size; /* Size of the resource */
|
||||
unsigned long limit; /* Largest valid value base + size -1 */
|
||||
unsigned long flags; /* Descriptions of the kind of resource */
|
||||
unsigned long index; /* Bus specific per device resource id */
|
||||
unsigned char align; /* Required alignment (base 2) of the resource */
|
||||
unsigned char gran; /* Granularity (base 2) of the resource */
|
||||
/* Alignment must be >= the granularity of the resource */
|
||||
};
|
||||
|
||||
#endif /* RESOURCE_H */
|
||||
|
|
@ -1,6 +1,14 @@
|
|||
#if 0
|
||||
#include <printk.h>
|
||||
#endif
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0
|
||||
};
|
||||
|
||||
void
|
||||
mainboard_fixup(void)
|
||||
|
|
@ -23,3 +31,107 @@ final_mainboard_fixup(void)
|
|||
//#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
struct ioapicreg {
|
||||
unsigned int reg;
|
||||
unsigned int value_low, value_high;
|
||||
};
|
||||
static struct ioapicreg ioapicregvalues[] = {
|
||||
#define ALL (0xff << 24)
|
||||
#define NONE (0)
|
||||
#define DISABLED (1 << 16)
|
||||
#define ENABLED (0 << 16)
|
||||
#define TRIGGER_EDGE (0 << 15)
|
||||
#define TRIGGER_LEVEL (1 << 15)
|
||||
#define POLARITY_HIGH (0 << 13)
|
||||
#define POLARITY_LOW (1 << 13)
|
||||
#define PHYSICAL_DEST (0 << 11)
|
||||
#define LOGICAL_DEST (1 << 11)
|
||||
#define ExtINT (7 << 8)
|
||||
#define NMI (4 << 8)
|
||||
#define SMI (2 << 8)
|
||||
#define INT (1 << 8)
|
||||
/* mask, trigger, polarity, destination, delivery, vector */
|
||||
{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
|
||||
{0x01, DISABLED, NONE},
|
||||
{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
|
||||
{0x03, DISABLED, NONE},
|
||||
{0x04, DISABLED, NONE},
|
||||
{0x05, DISABLED, NONE},
|
||||
{0x06, DISABLED, NONE},
|
||||
{0x07, DISABLED, NONE},
|
||||
{0x08, DISABLED, NONE},
|
||||
{0x09, DISABLED, NONE},
|
||||
{0x0a, DISABLED, NONE},
|
||||
{0x0b, DISABLED, NONE},
|
||||
{0x0c, DISABLED, NONE},
|
||||
{0x0d, DISABLED, NONE},
|
||||
{0x0e, DISABLED, NONE},
|
||||
{0x0f, DISABLED, NONE},
|
||||
{0x10, DISABLED, NONE},
|
||||
{0x11, DISABLED, NONE},
|
||||
{0x12, DISABLED, NONE},
|
||||
{0x13, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x15, DISABLED, NONE},
|
||||
{0x16, DISABLED, NONE},
|
||||
{0x17, DISABLED, NONE},
|
||||
{0x18, DISABLED, NONE},
|
||||
{0x19, DISABLED, NONE},
|
||||
{0x20, DISABLED, NONE},
|
||||
{0x21, DISABLED, NONE},
|
||||
{0x22, DISABLED, NONE},
|
||||
{0x23, DISABLED, NONE},
|
||||
};
|
||||
|
||||
static void setup_ioapic(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long value_low, value_high;
|
||||
unsigned long ioapic_base = 0xfec00000;
|
||||
volatile unsigned long *l;
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
l = (unsigned long *) ioapic_base;
|
||||
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
|
||||
i++, a++) {
|
||||
l[0] = (a->reg * 2) + 0x10;
|
||||
l[4] = a->value_low;
|
||||
value_low = l[4];
|
||||
l[0] = (a->reg *2) + 0x11;
|
||||
l[4] = a->value_high;
|
||||
value_high = l[4];
|
||||
if ((i==0) && (value_low == 0xffffffff)) {
|
||||
printk_warning("IO APIC not responding.\n");
|
||||
return;
|
||||
}
|
||||
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||
a->reg, a->value_low, a->value_high);
|
||||
}
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
printk_debug("lpc_init\n");
|
||||
#if 0
|
||||
pci_read_config_byte(dev, 0x4B, &byte);
|
||||
byte |= 1;
|
||||
pci_write_config_byte(dev, 0x4B, byte);
|
||||
setup_ioapic();
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x7468,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,118 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LNXI ";
|
||||
static const char productid[12] = "P4DPR ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "ISA ");
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
|
||||
/* ISA backward compatibility interrupts */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, 0x02, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x01, 0x02, 0x01);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, 0x02, 0x02);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x03, 0x02, 0x03);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x04, 0x02, 0x04);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x05, 0x02, 0x05);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x06, 0x02, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x07, 0x02, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
0x03, 0x08, 0x02, 0x08);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x09, 0x02, 0x09);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x0a, 0x02, 0x0a);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x03, 0x0b, 0x02, 0x0b);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0c, 0x02, 0x0c);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0d, 0x02, 0x0d);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0e, 0x02, 0x0e);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x0f, 0x02, 0x0f);
|
||||
|
||||
/* Standard local interrupt assignments */
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x03, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x00, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
|
||||
/* 8111 DevB.3 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x00, (5<<2)|3, 0x02, 0x13);
|
||||
|
||||
/* AGP Slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x01, (0<<2)|0, 0x02, 0x10);
|
||||
|
||||
/* PCI Slot 1 */
|
||||
/* PCI Slot 2 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (5 <<2)|0, 0x02, 0x11);
|
||||
/* PCI Slot 3 */
|
||||
/* PCI Slot 4 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (7<<2)|0, 0x02, 0x13);
|
||||
|
||||
/* AMR Slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
0x02, (1<<2)|0, 0x02, 0x10);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue