drivers/gic: reprogram the GIC CPU interface to bypass IRQ
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. So the CPU can exit from WFI when an asserted IRQ is coming. This is critical for power gating a CPU. BRANCH=none BUG=chrome-os-partner:39620 TEST=testing with CPU idle with power down state support and CPU can wake up normally Change-Id: I71ac642e28024a562db898665b74a5791fce325a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529 Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269116 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -26,6 +26,10 @@
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enum {
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ENABLE_GRP0 = 0x1 << 0,
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ENABLE_GRP1 = 0x1 << 1,
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FIQ_BYP_DIS_GRP0 = 0x1 << 5,
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IRQ_BYP_DIS_GRP0 = 0x1 << 6,
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FIQ_BYP_DIS_GRP1 = 0x1 << 7,
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IRQ_BYP_DIS_GRP1 = 0x1 << 8,
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};
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struct gic {
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@ -135,6 +139,13 @@ void gic_disable(void)
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/* Disable secure, non-secure interrupts. */
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uint32_t val = gic_read(&gicc->ctlr);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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/*
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* Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs.
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* So the CPU can wake up from power gating state when the GIC
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* was disabled.
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*/
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val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 |
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FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gic_write(&gicc->ctlr, val);
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}
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