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Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" 

In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2018-06-12 22:58:19 +02:00 committed by Patrick Georgi
parent 4dfb5f1055
commit 58a8953793
65 changed files with 363 additions and 295 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/model_2065x/bootblock.c
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@ -24,7 +24,6 @@
#include <cpu/intel/microcode/microcode.c> #include <cpu/intel/microcode/microcode.c>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h" #include "model_2065x.h"
#else #else

1
src/cpu/intel/model_206ax/bootblock.c
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@ -28,7 +28,6 @@
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */ /* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/rcba.h>
#else #else
#error "CPU must be paired with Intel BD82X6X or C216 southbridge" #error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif #endif

1
src/mainboard/apple/macbookair4_2/early_southbridge.c
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@ -25,7 +25,6 @@
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h" #include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>

1
src/mainboard/apple/macbookair4_2/mainboard.c
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@ -13,7 +13,6 @@
#include <device/device.h> #include <device/device.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/compulab/intense_pc/romstage.c
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@ -18,7 +18,6 @@
#include <arch/io.h> #include <arch/io.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include "northbridge/intel/sandybridge/raminit_native.h"
#include <superio/smsc/sio1007/chip.h> #include <superio/smsc/sio1007/chip.h>
#include <southbridge/intel/common/rcba.h>
#define SIO_PORT 0x164e #define SIO_PORT 0x164e

1
src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
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@ -27,7 +27,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h> #include <smbios.h>
#include <device/pci.h> #include <device/pci.h>

1
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
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@ -28,7 +28,6 @@
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
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@ -27,7 +27,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h> #include <smbios.h>
#include <device/pci.h> #include <device/pci.h>

1
src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
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@ -28,7 +28,6 @@
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

5
src/mainboard/google/butterfly/romstage.c
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@ -29,7 +29,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -96,9 +95,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
/* Disable unused devices (board specific) */ /* Disable unused devices (board specific) */
reg32 = RCBA32(FD); reg32 = RCBA32(FD);

5
src/mainboard/google/link/romstage.c
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@ -30,7 +30,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include "ec/google/chromeec/ec.h" #include "ec/google/chromeec/ec.h"
#include <arch/cpu.h> #include <arch/cpu.h>
@ -104,9 +103,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
} }
static uint8_t *locate_spd(void) static uint8_t *locate_spd(void)

5
src/mainboard/google/parrot/romstage.c
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@ -29,7 +29,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -95,9 +94,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
/* Disable unused devices (board specific) */ /* Disable unused devices (board specific) */
reg32 = RCBA32(FD); reg32 = RCBA32(FD);

5
src/mainboard/google/stout/romstage.c
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@ -29,7 +29,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -101,9 +100,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
/* Disable unused devices (board specific) */ /* Disable unused devices (board specific) */
reg32 = RCBA32(FD); reg32 = RCBA32(FD);

1
src/mainboard/hp/folio_9470m/romstage.c
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@ -18,7 +18,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <ec/hp/kbc1126/ec.h> #include <ec/hp/kbc1126/ec.h>

1
src/mainboard/hp/revolve_810_g1/romstage.c
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@ -21,7 +21,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <ec/hp/kbc1126/ec.h> #include <ec/hp/kbc1126/ec.h>

2
src/mainboard/intel/dcp847ske/early_southbridge.c
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@ -23,7 +23,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include "northbridge/intel/sandybridge/raminit_native.h" #include "northbridge/intel/sandybridge/raminit_native.h"
#include <southbridge/intel/common/rcba.h>
#include "superio.h" #include "superio.h"
#include "thermal.h" #include "thermal.h"

1
src/mainboard/intel/emeraldlake2/romstage.c
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@ -31,7 +31,6 @@
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>

1
src/mainboard/kontron/ktqm77/romstage.c
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@ -29,7 +29,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/mainboard/lenovo/l520/romstage.c
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@ -20,7 +20,6 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>

1
src/mainboard/lenovo/s230u/romstage.c
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@ -27,7 +27,6 @@
#include <console/console.h> #include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h" #include "northbridge/intel/sandybridge/raminit_native.h"
#include <southbridge/intel/common/rcba.h>
#include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/mainboard/lenovo/t420/romstage.c
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@ -17,7 +17,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/lenovo/t420s/romstage.c
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@ -19,7 +19,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/lenovo/t430s/romstage.c
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@ -20,7 +20,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)

1
src/mainboard/lenovo/t520/romstage.c
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@ -30,7 +30,6 @@
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

2
src/mainboard/lenovo/t530/romstage.c
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@ -21,7 +21,7 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <device/device.h> #include <device/device.h>

1
src/mainboard/lenovo/x201/mainboard.c
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@ -21,7 +21,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>

1
src/mainboard/lenovo/x201/romstage.c
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@ -39,7 +39,6 @@
#include "dock.h" #include "dock.h"
#include "arch/early_variables.h" #include "arch/early_variables.h"
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>

1
src/mainboard/lenovo/x220/romstage.c
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@ -29,7 +29,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/mainboard/lenovo/x230/romstage.c
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@ -30,7 +30,6 @@
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/mainboard/packardbell/ms2290/romstage.c
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@ -37,7 +37,6 @@
#include <cbmem.h> #include <cbmem.h>
#include "arch/early_variables.h" #include "arch/early_variables.h"
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/pch.h>
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>

1
src/mainboard/roda/rv11/romstage.c
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@ -14,7 +14,6 @@
*/ */
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
void mainboard_rcba_config(void) void mainboard_rcba_config(void)

1
src/mainboard/roda/rv11/variants/rv11/romstage.c
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@ -18,7 +18,6 @@
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)

5
src/mainboard/samsung/lumpy/romstage.c
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@ -32,7 +32,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -103,9 +102,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
} }
static const uint8_t *locate_spd(void) static const uint8_t *locate_spd(void)

5
src/mainboard/samsung/stumpy/romstage.c
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@ -32,7 +32,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -112,9 +111,9 @@ void mainboard_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
} }
static void setup_sio_gpios(void) static void setup_sio_gpios(void)

1
src/mainboard/sapphire/pureplatinumh61/mainboard.c
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@ -17,7 +17,6 @@
#include <device/device.h> #include <device/device.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/rcba.h>
static void mainboard_init(struct device *dev) static void mainboard_init(struct device *dev)
{ {

1
src/mainboard/sapphire/pureplatinumh61/romstage.c
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@ -27,7 +27,6 @@
#include <console/console.h> #include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h" #include "northbridge/intel/sandybridge/raminit_native.h"
#include <southbridge/intel/common/rcba.h>
#include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>

1
src/northbridge/intel/nehalem/early_init.c
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@ -25,7 +25,6 @@
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <southbridge/intel/common/rcba.h>
#include "nehalem.h" #include "nehalem.h"

1
src/northbridge/intel/nehalem/nehalem.h
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@ -168,7 +168,6 @@ typedef struct {
#define QUICKPATH_BUS 0xff #define QUICKPATH_BUS 0xff
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/pch.h>
/* Everything below this line is ignored in the DSDT */ /* Everything below this line is ignored in the DSDT */

1
src/northbridge/intel/nehalem/raminit.c
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@ -56,7 +56,6 @@ typedef u32 device_t;
#include "nehalem.h" #include "nehalem.h"
#include <southbridge/intel/common/rcba.h>
#include "southbridge/intel/ibexpeak/me.h" #include "southbridge/intel/ibexpeak/me.h"
#if REAL #if REAL

1
src/northbridge/intel/sandybridge/early_init.c
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@ -24,7 +24,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <southbridge/intel/common/rcba.h>
#include "sandybridge.h" #include "sandybridge.h"
static void sandybridge_setup_bars(void) static void sandybridge_setup_bars(void)

1
src/northbridge/intel/sandybridge/sandybridge.h
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@ -59,7 +59,6 @@
#define IOMMU_BASE2 0xfed91000ULL #define IOMMU_BASE2 0xfed91000ULL
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/rcba.h>
/* Everything below this line is ignored in the DSDT */ /* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__ #ifndef __ACPI__

1
src/southbridge/intel/bd82x6x/azalia.c
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@ -23,7 +23,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
#include <device/azalia_device.h> #include <device/azalia_device.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#define HDA_ICII_REG 0x68 #define HDA_ICII_REG 0x68

1
src/southbridge/intel/bd82x6x/bootblock.c
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@ -15,7 +15,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include "southbridge/intel/common/rcba.h"
#include "pch.h" #include "pch.h"
static void store_initial_timestamp(void) static void store_initial_timestamp(void)

1
src/southbridge/intel/bd82x6x/early_pch.c
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@ -24,7 +24,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
/* For DMI bar. */ /* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"

5
src/southbridge/intel/bd82x6x/early_rcba.c
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@ -17,7 +17,6 @@
#include <stdint.h> #include <stdint.h>
#include "pch.h" #include "pch.h"
#include <southbridge/intel/common/rcba.h>
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"
void void
@ -60,9 +59,9 @@ southbridge_configure_default_intmap(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */ /* Enable IOAPIC (generic) */
RCBA16(EOIC) = 0x0100; RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */ /* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(EOIC); (void) RCBA16(OIC);
} }
void void

1
src/southbridge/intel/bd82x6x/early_spi.c
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@ -19,7 +19,6 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#define SPI_DELAY 10 /* 10us */ #define SPI_DELAY 10 /* 10us */

1
src/southbridge/intel/bd82x6x/early_thermal.c
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@ -16,7 +16,6 @@
#include <arch/io.h> #include <arch/io.h>
#include "pch.h" #include "pch.h"
#include <southbridge/intel/common/rcba.h>
#include "cpu/intel/model_206ax/model_206ax.h" #include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>

2
src/southbridge/intel/bd82x6x/finalize.c
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@ -18,7 +18,7 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/post_codes.h> #include <console/post_codes.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <southbridge/intel/common/rcba.h> #include "pch.h"
#include <spi-generic.h> #include <spi-generic.h>
#include "chip.h" #include "chip.h"
#include "pch.h" #include "pch.h"

1
src/southbridge/intel/bd82x6x/lpc.c
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@ -33,7 +33,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <string.h> #include <string.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#include "nvs.h" #include "nvs.h"
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>

1
src/southbridge/intel/bd82x6x/me.c
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@ -39,7 +39,6 @@
# include <device/pci.h> # include <device/pci.h>
#endif #endif
#include <southbridge/intel/common/rcba.h>
#include "me.h" #include "me.h"
#include "pch.h" #include "pch.h"

1
src/southbridge/intel/bd82x6x/me_8.x.c
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@ -39,7 +39,6 @@
# include <device/pci.h> # include <device/pci.h>
#endif #endif
#include <southbridge/intel/common/rcba.h>
#include "me.h" #include "me.h"
#include "pch.h" #include "pch.h"

1
src/southbridge/intel/bd82x6x/pch.c
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@ -24,7 +24,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#endif #endif
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#include <string.h> #include <string.h>

149
src/southbridge/intel/bd82x6x/pch.h
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@ -45,6 +45,12 @@
#define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500 #define DEFAULT_PMBASE 0x0500
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
#define CROS_GPIO_DEVICE_NAME "CougarPoint" #define CROS_GPIO_DEVICE_NAME "CougarPoint"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
@ -264,6 +270,73 @@ int rtc_failure(void);
/* Root Complex Register Block */ /* Root Complex Register Block */
#define RCBA 0xf0 #define RCBA 0xf0
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */
#define PVC 0x000c /* 16bit */
#define PVS 0x000e /* 16bit */
#define V0CAP 0x0010 /* 32bit */
#define V0CTL 0x0014 /* 32bit */
#define V0STS 0x001a /* 16bit */
#define V1CAP 0x001c /* 32bit */
#define V1CTL 0x0020 /* 32bit */
#define V1STS 0x0026 /* 16bit */
#define RCTCL 0x0100 /* 32bit */
#define ESD 0x0104 /* 32bit */
#define ULD 0x0110 /* 32bit */
#define ULBA 0x0118 /* 64bit */
#define RP1D 0x0120 /* 32bit */
#define RP1BA 0x0128 /* 64bit */
#define RP2D 0x0130 /* 32bit */
#define RP2BA 0x0138 /* 64bit */
#define RP3D 0x0140 /* 32bit */
#define RP3BA 0x0148 /* 64bit */
#define RP4D 0x0150 /* 32bit */
#define RP4BA 0x0158 /* 64bit */
#define HDD 0x0160 /* 32bit */
#define HDBA 0x0168 /* 64bit */
#define RP5D 0x0170 /* 32bit */
#define RP5BA 0x0178 /* 64bit */
#define RP6D 0x0180 /* 32bit */
#define RP6BA 0x0188 /* 64bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */
#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
/* Get the function number assigned to a Root Port */
#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
/* Set the function number for a Root Port */
#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
/* Root Port function number mask */
#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
#define IOTR0 0x1e80 /* 64bit */
#define IOTR1 0x1e88 /* 64bit */
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
#define TCTL 0x3000 /* 8bit */
#define NOINT 0 #define NOINT 0
#define INTA 1 #define INTA 1
@ -293,9 +366,85 @@ int rtc_failure(void);
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
#define D31IP_SIP2 20 /* SATA Pin 2 */
#define D31IP_SMIP 12 /* SMBUS Pin */
#define D31IP_SIP 8 /* SATA Pin */
#define D30IP 0x3104 /* 32bit */
#define D30IP_PIP 0 /* PCI Bridge Pin */
#define D29IP 0x3108 /* 32bit */
#define D29IP_E1P 0 /* EHCI #1 Pin */
#define D28IP 0x310c /* 32bit */
#define D28IP_P8IP 28 /* PCI Express Port 8 */
#define D28IP_P7IP 24 /* PCI Express Port 7 */
#define D28IP_P6IP 20 /* PCI Express Port 6 */
#define D28IP_P5IP 16 /* PCI Express Port 5 */
#define D28IP_P4IP 12 /* PCI Express Port 4 */
#define D28IP_P3IP 8 /* PCI Express Port 3 */
#define D28IP_P2IP 4 /* PCI Express Port 2 */
#define D28IP_P1IP 0 /* PCI Express Port 1 */
#define D27IP 0x3110 /* 32bit */
#define D27IP_ZIP 0 /* HD Audio Pin */
#define D26IP 0x3114 /* 32bit */
#define D26IP_E2P 0 /* EHCI #2 Pin */
#define D25IP 0x3118 /* 32bit */
#define D25IP_LIP 0 /* GbE LAN Pin */
#define D22IP 0x3124 /* 32bit */
#define D22IP_KTIP 12 /* KT Pin */
#define D22IP_IDERIP 8 /* IDE-R Pin */
#define D22IP_MEI2IP 4 /* MEI #2 Pin */
#define D22IP_MEI1IP 0 /* MEI #1 Pin */
#define D20IP 0x3128 /* 32bit */
#define D20IP_XHCIIP 0
#define D31IR 0x3140 /* 16bit */
#define D30IR 0x3142 /* 16bit */
#define D29IR 0x3144 /* 16bit */
#define D28IR 0x3146 /* 16bit */
#define D27IR 0x3148 /* 16bit */
#define D26IR 0x314c /* 16bit */
#define D25IR 0x3150 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define D20IR 0x3160 /* 16bit */
#define OIC 0x31fe /* 16bit */
#define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8 #define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(x,a,b,c,d) \
RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
#define GCS 0x3410 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
#define PCH_DISABLE_P2P (1 << 1)
#define PCH_DISABLE_SATA1 (1 << 2)
#define PCH_DISABLE_SMBUS (1 << 3)
#define PCH_DISABLE_HD_AUDIO (1 << 4)
#define PCH_DISABLE_EHCI2 (1 << 13)
#define PCH_DISABLE_LPC (1 << 14)
#define PCH_DISABLE_EHCI1 (1 << 15)
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
#define PCH_DISABLE_THERMAL (1 << 24)
#define PCH_DISABLE_SATA2 (1 << 25)
#define PCH_DISABLE_XHCI (1 << 27)
/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT (1 << 4)
#define PCH_DISABLE_IDER (1 << 3)
#define PCH_DISABLE_MEI2 (1 << 2)
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
/* USB Port Disable Override */ /* USB Port Disable Override */
#define USBPDO 0x359c /* 32bit */ #define USBPDO 0x359c /* 32bit */
/* USB Overcurrent MAP Register */ /* USB Overcurrent MAP Register */

1
src/southbridge/intel/bd82x6x/pcie.c
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@ -21,7 +21,6 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <assert.h> #include <assert.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
static void pch_pcie_pm_early(struct device *dev) static void pch_pcie_pm_early(struct device *dev)

1
src/southbridge/intel/bd82x6x/smihandler.c
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@ -23,7 +23,6 @@
#include <elog.h> #include <elog.h>
#include <halt.h> #include <halt.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#include "nvs.h" #include "nvs.h"

1
src/southbridge/intel/bd82x6x/usb_ehci.c
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@ -18,7 +18,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include <arch/io.h> #include <arch/io.h>

220
src/southbridge/intel/common/rcba.h
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@ -1,220 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
/*
* The DnnIR registers use common RCBA offsets across these chipsets:
* bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
*
* However not all registers are in use on all of these.
*/
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#ifndef __ACPI__
#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
#define RCBA_AND_OR(bits, x, and, or) \
(RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */
#define PVC 0x000c /* 16bit */
#define PVS 0x000e /* 16bit */
#define V0CAP 0x0010 /* 32bit */
#define V0CTL 0x0014 /* 32bit */
#define V0STS 0x001a /* 16bit */
#define V1CAP 0x001c /* 32bit */
#define V1CTL 0x0020 /* 32bit */
#define V1STS 0x0026 /* 16bit */
#define RCTCL 0x0100 /* 32bit */
#define ESD 0x0104 /* 32bit */
#define ULD 0x0110 /* 32bit */
#define ULBA 0x0118 /* 64bit */
#define RP1D 0x0120 /* 32bit */
#define RP1BA 0x0128 /* 64bit */
#define RP2D 0x0130 /* 32bit */
#define RP2BA 0x0138 /* 64bit */
#define RP3D 0x0140 /* 32bit */
#define RP3BA 0x0148 /* 64bit */
#define RP4D 0x0150 /* 32bit */
#define RP4BA 0x0158 /* 64bit */
#define HDD 0x0160 /* 32bit */
#define HDBA 0x0168 /* 64bit */
#define RP5D 0x0170 /* 32bit */
#define RP5BA 0x0178 /* 64bit */
#define RP6D 0x0180 /* 32bit */
#define RP6BA 0x0188 /* 64bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */
#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
/* Get the function number assigned to a Root Port */
#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)
/* Set the function number for a Root Port */
#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))
/* Root Port function number mask */
#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
#define IOTR0 0x1e80 /* 64bit */
#define IOTR1 0x1e88 /* 64bit */
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
#define TCTL 0x3000 /* 8bit */
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
#define D31IP_SIP2 20 /* SATA Pin 2 */
#define D31IP_SMIP 12 /* SMBUS Pin */
#define D31IP_SIP 8 /* SATA Pin */
#define D30IP 0x3104 /* 32bit */
#define D30IP_PIP 0 /* PCI Bridge Pin */
#define D29IP 0x3108 /* 32bit */
#define D29IP_E1P 0 /* EHCI #1 Pin */
#define D28IP 0x310c /* 32bit */
#define D28IP_P8IP 28 /* PCI Express Port 8 */
#define D28IP_P7IP 24 /* PCI Express Port 7 */
#define D28IP_P6IP 20 /* PCI Express Port 6 */
#define D28IP_P5IP 16 /* PCI Express Port 5 */
#define D28IP_P4IP 12 /* PCI Express Port 4 */
#define D28IP_P3IP 8 /* PCI Express Port 3 */
#define D28IP_P2IP 4 /* PCI Express Port 2 */
#define D28IP_P1IP 0 /* PCI Express Port 1 */
#define D27IP 0x3110 /* 32bit */
#define D27IP_ZIP 0 /* HD Audio Pin */
#define D26IP 0x3114 /* 32bit */
#define D26IP_E2P 0 /* EHCI #2 Pin */
#define D25IP 0x3118 /* 32bit */
#define D25IP_LIP 0 /* GbE LAN Pin */
#define D22IP 0x3124 /* 32bit */
#define D22IP_KTIP 12 /* KT Pin */
#define D22IP_IDERIP 8 /* IDE-R Pin */
#define D22IP_MEI2IP 4 /* MEI #2 Pin */
#define D22IP_MEI1IP 0 /* MEI #1 Pin */
#define D20IP 0x3128 /* 32bit */
#define D20IP_XHCIIP 0
#define D31IR 0x3140 /* 16bit */
#define D30IR 0x3142 /* 16bit */
#define D29IR 0x3144 /* 16bit */
#define D28IR 0x3146 /* 16bit */
#define D27IR 0x3148 /* 16bit */
#define D26IR 0x314c /* 16bit */
#define D25IR 0x3150 /* 16bit */
#define D23IR 0x3158 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define D21IR 0x3164 /* 16bit */
#define D20IR 0x3160 /* 16bit */
#define D19IR 0x3168 /* 16bit */
#define EOIC 0x31fe /* 16bit */
#define OIC 0x31ff /* 8bit */
#define DIR_ROUTE(x, a, b, c, d) \
(RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR)))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
#define GCS 0x3410 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
#define PCH_DISABLE_P2P (1 << 1)
#define PCH_DISABLE_SATA1 (1 << 2)
#define PCH_DISABLE_SMBUS (1 << 3)
#define PCH_DISABLE_HD_AUDIO (1 << 4)
#define PCH_DISABLE_EHCI2 (1 << 13)
#define PCH_DISABLE_LPC (1 << 14)
#define PCH_DISABLE_EHCI1 (1 << 15)
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
#define PCH_DISABLE_THERMAL (1 << 24)
#define PCH_DISABLE_SATA2 (1 << 25)
#define PCH_DISABLE_XHCI (1 << 27)
/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT (1 << 4)
#define PCH_DISABLE_IDER (1 << 3)
#define PCH_DISABLE_MEI2 (1 << 2)
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
/* Function Disable (FD) register values.
* Setting a bit disables the corresponding
* feature.
* Not all features might be disabled on
* all chipsets. Esp. ICH-7U is picky.
*/
#define FD_PCIE6 (1 << 21)
#define FD_PCIE5 (1 << 20)
#define FD_PCIE4 (1 << 19)
#define FD_PCIE3 (1 << 18)
#define FD_PCIE2 (1 << 17)
#define FD_PCIE1 (1 << 16)
#define FD_EHCI (1 << 15)
#define FD_LPCB (1 << 14)
/* UHCI must be disabled from 4 downwards.
* If UHCI controllers get disabled, EHCI
* must know about it, too! */
#define FD_UHCI4 (1 << 11)
#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
#define FD_INTLAN (1 << 7)
#define FD_ACMOD (1 << 6)
#define FD_ACAUD (1 << 5)
#define FD_HDAUD (1 << 4)
#define FD_SMBUS (1 << 3)
#define FD_SATA (1 << 2)
#define FD_PATA (1 << 1)
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */

2
src/southbridge/intel/common/rcba_pirq.c
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@ -17,7 +17,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/rcba_pirq.h>
#define MAX_SLOT 31 #define MAX_SLOT 31
#define MIN_SLOT 19 #define MIN_SLOT 19

44
src/southbridge/intel/common/rcba_pirq.h Normal file
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@ -0,0 +1,44 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
#define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
/*
* The DnnIR registers use common RCBA offsets across these chipsets:
* bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
*
* However not all registers are in use on all of these.
*/
#define D31IR 0x3140 /* 16bit */
#define D30IR 0x3142 /* 16bit */
#define D29IR 0x3144 /* 16bit */
#define D28IR 0x3146 /* 16bit */
#define D27IR 0x3148 /* 16bit */
#define D26IR 0x314c /* 16bit */
#define D25IR 0x3150 /* 16bit */
#define D23IR 0x3158 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define D21IR 0x3164 /* 16bit */
#define D20IR 0x3160 /* 16bit */
#define D19IR 0x3168 /* 16bit */
#define DEFAULT_RCBA 0xfed1c000
#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))
#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */

1
src/southbridge/intel/ibexpeak/azalia.c
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@ -23,7 +23,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
#include <device/azalia_device.h> #include <device/azalia_device.h>
#include <southbridge/intel/common/rcba.h>
#include "pch.h" #include "pch.h"
#define HDA_ICII_REG 0x68 #define HDA_ICII_REG 0x68

1
src/southbridge/intel/ibexpeak/lpc.c
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@ -36,7 +36,6 @@
#include "nvs.h" #include "nvs.h"
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/rcba.h>
#define NMI_OFF 0 #define NMI_OFF 0

1
src/southbridge/intel/ibexpeak/me.c
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@ -30,7 +30,6 @@
#include <string.h> #include <string.h>
#include <delay.h> #include <delay.h>
#include <elog.h> #include <elog.h>
#include <southbridge/intel/common/rcba.h>
#ifdef __SMM__ #ifdef __SMM__
#include <arch/io.h> #include <arch/io.h>

152
src/southbridge/intel/ibexpeak/pch.h
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@ -46,6 +46,12 @@
#define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500 #define DEFAULT_PMBASE 0x0500
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#ifndef __ACPI__ #ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0 #define DEBUG_PERIODIC_SMIS 0
@ -235,6 +241,75 @@ void southbridge_configure_default_intmap(void);
/* Root Complex Register Block */ /* Root Complex Register Block */
#define RCBA 0xf0 #define RCBA 0xf0
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */
#define PVC 0x000c /* 16bit */
#define PVS 0x000e /* 16bit */
#define V0CAP 0x0010 /* 32bit */
#define V0CTL 0x0014 /* 32bit */
#define V0STS 0x001a /* 16bit */
#define V1CAP 0x001c /* 32bit */
#define V1CTL 0x0020 /* 32bit */
#define V1STS 0x0026 /* 16bit */
#define RCTCL 0x0100 /* 32bit */
#define ESD 0x0104 /* 32bit */
#define ULD 0x0110 /* 32bit */
#define ULBA 0x0118 /* 64bit */
#define RP1D 0x0120 /* 32bit */
#define RP1BA 0x0128 /* 64bit */
#define RP2D 0x0130 /* 32bit */
#define RP2BA 0x0138 /* 64bit */
#define RP3D 0x0140 /* 32bit */
#define RP3BA 0x0148 /* 64bit */
#define RP4D 0x0150 /* 32bit */
#define RP4BA 0x0158 /* 64bit */
#define HDD 0x0160 /* 32bit */
#define HDBA 0x0168 /* 64bit */
#define RP5D 0x0170 /* 32bit */
#define RP5BA 0x0178 /* 64bit */
#define RP6D 0x0180 /* 32bit */
#define RP6BA 0x0188 /* 64bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */
#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
/* Get the function number assigned to a Root Port */
#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
/* Set the function number for a Root Port */
#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
/* Root Port function number mask */
#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
#define IOTR0 0x1e80 /* 64bit */
#define IOTR1 0x1e88 /* 64bit */
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
#define TCTL 0x3000 /* 8bit */
#define NOINT 0 #define NOINT 0
#define INTA 1 #define INTA 1
#define INTB 2 #define INTB 2
@ -263,9 +338,86 @@ void southbridge_configure_default_intmap(void);
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
#define D31IP_SIP2 20 /* SATA Pin 2 */
#define D31IP_UNKIP 16
#define D31IP_SMIP 12 /* SMBUS Pin */
#define D31IP_SIP 8 /* SATA Pin */
#define D30IP 0x3104 /* 32bit */
#define D30IP_PIP 0 /* PCI Bridge Pin */
#define D29IP 0x3108 /* 32bit */
#define D29IP_E1P 0 /* EHCI #1 Pin */
#define D28IP 0x310c /* 32bit */
#define D28IP_P8IP 28 /* PCI Express Port 8 */
#define D28IP_P7IP 24 /* PCI Express Port 7 */
#define D28IP_P6IP 20 /* PCI Express Port 6 */
#define D28IP_P5IP 16 /* PCI Express Port 5 */
#define D28IP_P4IP 12 /* PCI Express Port 4 */
#define D28IP_P3IP 8 /* PCI Express Port 3 */
#define D28IP_P2IP 4 /* PCI Express Port 2 */
#define D28IP_P1IP 0 /* PCI Express Port 1 */
#define D27IP 0x3110 /* 32bit */
#define D27IP_ZIP 0 /* HD Audio Pin */
#define D26IP 0x3114 /* 32bit */
#define D26IP_E2P 0 /* EHCI #2 Pin */
#define D25IP 0x3118 /* 32bit */
#define D25IP_LIP 0 /* GbE LAN Pin */
#define D22IP 0x3124 /* 32bit */
#define D22IP_KTIP 12 /* KT Pin */
#define D22IP_IDERIP 8 /* IDE-R Pin */
#define D22IP_MEI2IP 4 /* MEI #2 Pin */
#define D22IP_MEI1IP 0 /* MEI #1 Pin */
#define D20IP 0x3128 /* 32bit */
#define D20IP_XHCIIP 0
#define D31IR 0x3140 /* 16bit */
#define D30IR 0x3142 /* 16bit */
#define D29IR 0x3144 /* 16bit */
#define D28IR 0x3146 /* 16bit */
#define D27IR 0x3148 /* 16bit */
#define D26IR 0x314c /* 16bit */
#define D25IR 0x3150 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define D20IR 0x3160 /* 16bit */
#define OIC 0x31fe /* 16bit */
#define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8 #define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
#define GCS 0x3410 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
#define PCH_DISABLE_P2P (1 << 1)
#define PCH_DISABLE_SATA1 (1 << 2)
#define PCH_DISABLE_SMBUS (1 << 3)
#define PCH_DISABLE_HD_AUDIO (1 << 4)
#define PCH_DISABLE_EHCI2 (1 << 13)
#define PCH_DISABLE_LPC (1 << 14)
#define PCH_DISABLE_EHCI1 (1 << 15)
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
#define PCH_DISABLE_THERMAL (1 << 24)
#define PCH_DISABLE_SATA2 (1 << 25)
#define PCH_DISABLE_XHCI (1 << 27)
/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT (1 << 4)
#define PCH_DISABLE_IDER (1 << 3)
#define PCH_DISABLE_MEI2 (1 << 2)
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
/* ICH7 PMBASE */ /* ICH7 PMBASE */
#define PM1_STS 0x00 #define PM1_STS 0x00
#define WAK_STS (1 << 15) #define WAK_STS (1 << 15)

1
src/southbridge/intel/ibexpeak/smihandler.c
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@ -24,7 +24,6 @@
#include <halt.h> #include <halt.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include "pch.h" #include "pch.h"
#include <southbridge/intel/common/rcba.h>
#include "nvs.h" #include "nvs.h"

1
src/southbridge/intel/ibexpeak/usb_ehci.c
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@ -22,7 +22,6 @@
#include "pch.h" #include "pch.h"
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include <arch/io.h> #include <arch/io.h>
#include <southbridge/intel/common/rcba.h>
static void usb_ehci_init(struct device *dev) static void usb_ehci_init(struct device *dev)
{ {