siemens/mc_apl3: Add new mainboard variant mc_apl3
This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl3 mainboard will follow in separate commits. Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
Philipp Deppenwiese
parent
e63a5f1e7f
commit
58bf3e7632
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@ -18,11 +18,13 @@ config VARIANT_DIR
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string
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default "mc_apl1" if BOARD_SIEMENS_MC_APL1
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default "mc_apl2" if BOARD_SIEMENS_MC_APL2
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default "mc_apl3" if BOARD_SIEMENS_MC_APL3
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config MAINBOARD_PART_NUMBER
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string
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default "MC APL1" if BOARD_SIEMENS_MC_APL1
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default "MC APL2" if BOARD_SIEMENS_MC_APL2
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default "MC APL3" if BOARD_SIEMENS_MC_APL3
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config MAX_CPUS
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int
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@ -5,3 +5,7 @@ config BOARD_SIEMENS_MC_APL1
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config BOARD_SIEMENS_MC_APL2
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bool "-> MC APL2"
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select BOARD_SIEMENS_BASEBOARD_MC_APL1
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config BOARD_SIEMENS_MC_APL3
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bool "-> MC APL3"
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select BOARD_SIEMENS_BASEBOARD_MC_APL1
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@ -0,0 +1,16 @@
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if BOARD_SIEMENS_MC_APL3
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config BOARD_SIEMENS_MC_APL3_VAR
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def_bool y
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select DRIVER_INTEL_I210
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select DRIVERS_I2C_RX6110SA
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select DRIVER_SIEMENS_NC_FPGA
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select NC_FPGA_NOTIFY_CB_READY
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select APL_SKIP_SET_POWER_LIMITS
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config DEVICETREE
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string
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default "variants/mc_apl3/devicetree.cb"
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endif # BOARD_SIEMENS_MC_APL3
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@ -0,0 +1 @@
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ramstage-y += mainboard.c
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@ -0,0 +1,119 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "sci_irq" = "SCIS_IRQ10"
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# Disable unused clkreq of PCIe root ports
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register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
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register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
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register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
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register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
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register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C16"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28162828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181717"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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# 0:HS400(Default), 1:HS200, 2:DDR50
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register "emmc_host_max_speed" = "2"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Proximity Sensor |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_STANDARD
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},
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}"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 off end # - DPTF
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device pci 00.2 off end # - NPK
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device pci 02.0 on end # - Gen - Display
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device pci 03.0 off end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 off end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 off end # - Shared SRAM
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device pci 0e.0 off end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 on end # - SATA
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device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY
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device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY
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device pci 13.2 off end # - RP 4 - PCIe-A 2
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device pci 13.3 off end # - RP 5 - PCIe-A 3
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device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
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device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on # - I2C 0
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# Enable external RTC chip
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chip drivers/i2c/rx6110sa
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register "pmon_sampling" = "PMON_SAMPL_256_MS"
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register "bks_on" = "0"
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register "bks_off" = "1"
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register "iocut_en" = "1"
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register "set_user_date" = "1"
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register "user_year" = "04"
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register "user_month" = "07"
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register "user_day" = "01"
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register "user_weekday" = "4"
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device i2c 0x32 on end # RTC RX6110 SA
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end
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end
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device pci 16.1 off end # - I2C 1
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device pci 16.2 off end # - I2C 2
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device pci 16.3 off end # - I2C 3
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device pci 17.0 off end # - I2C 4
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device pci 17.1 off end # - I2C 5
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device pci 17.2 off end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 off end # - SPI 0
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device pci 19.1 off end # - SPI 1
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device pci 19.2 off end # - SPI 2
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device pci 1a.0 off end # - PWM
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device pci 1b.0 off end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1d.0 off end # - UFS
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on end # - LPC
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device pci 1f.1 on end # - SMBUS
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end
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end
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@ -0,0 +1,98 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <gpio.h>
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#include <hwilib.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <baseboard/variants.h>
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#define TX_DWORD3 0xa8c
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void variant_mainboard_final(void)
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{
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struct device *dev = NULL;
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/*
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* PIR6 register mapping for PCIe root ports
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* INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
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*/
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pcr_write16(PID_ITSS, 0x314c, 0x0321);
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/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
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dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
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if (dev)
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pci_write_config8(dev, 0xd8, 0x3e);
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/* Enable CLKRUN_EN for power gating LPC */
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lpc_enable_pci_clk_cntl();
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/*
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* Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
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* offset 0x341D bit3 and bit0.
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* Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
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* offset 0x341C bit [3:0].
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*/
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pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
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/*
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* Correct the SATA transmit signal via the High Speed I/O Transmit
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* Control Register 3.
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* Bit [23:16] set the output voltage swing for TX line.
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* The value 0x4a sets the swing level to 0.58 V.
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*/
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pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
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}
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static void wait_for_legacy_dev(void *unused)
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{
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uint32_t legacy_delay, us_since_boot;
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struct stopwatch sw;
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/* Open main hwinfo block. */
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if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
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return;
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/* Get legacy delay parameter from hwinfo. */
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if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
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sizeof(legacy_delay)) != sizeof(legacy_delay))
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return;
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us_since_boot = get_us_since_boot();
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/* No need to wait if the time since boot is already long enough.*/
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if (us_since_boot > legacy_delay)
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return;
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stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
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printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
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legacy_delay - us_since_boot, legacy_delay);
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stopwatch_wait_until_expired(&sw);
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printk(BIOS_NOTICE, "done!\n");
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}
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static void finalize_boot(void *unused)
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{
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/* Set coreboot ready LED. */
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gpio_output(CNV_RGI_DT, 1);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
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