siemens/mc_apl3: Add new mainboard variant mc_apl3

This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl3 mainboard will follow in separate commits.

Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/mainboard/siemens/mc_apl1/Kconfig

@@ -18,11 +18,13 @@ config VARIANT_DIR
 	string
 	default "mc_apl1" if BOARD_SIEMENS_MC_APL1
 	default "mc_apl2" if BOARD_SIEMENS_MC_APL2
+	default "mc_apl3" if BOARD_SIEMENS_MC_APL3
 
 config MAINBOARD_PART_NUMBER
 	string
 	default "MC APL1" if BOARD_SIEMENS_MC_APL1
 	default "MC APL2" if BOARD_SIEMENS_MC_APL2
+	default "MC APL3" if BOARD_SIEMENS_MC_APL3
 
 config MAX_CPUS
 	int

src/mainboard/siemens/mc_apl1/Kconfig.name

@@ -5,3 +5,7 @@ config BOARD_SIEMENS_MC_APL1
 config BOARD_SIEMENS_MC_APL2
 	bool "-> MC APL2"
 	select BOARD_SIEMENS_BASEBOARD_MC_APL1
+
+config BOARD_SIEMENS_MC_APL3
+	bool "-> MC APL3"
+	select BOARD_SIEMENS_BASEBOARD_MC_APL1

src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig

@@ -0,0 +1,16 @@
+
+if BOARD_SIEMENS_MC_APL3
+
+config BOARD_SIEMENS_MC_APL3_VAR
+	def_bool y
+	select DRIVER_INTEL_I210
+	select DRIVERS_I2C_RX6110SA
+	select DRIVER_SIEMENS_NC_FPGA
+	select NC_FPGA_NOTIFY_CB_READY
+	select APL_SKIP_SET_POWER_LIMITS
+
+config DEVICETREE
+	string
+	default "variants/mc_apl3/devicetree.cb"
+
+endif # BOARD_SIEMENS_MC_APL3

src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc

@@ -0,0 +1 @@
+ramstage-y += mainboard.c

src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb

@@ -0,0 +1,119 @@
+chip soc/intel/apollolake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	register "sci_irq" = "SCIS_IRQ10"
+
+	# Disable unused clkreq of PCIe root ports
+	register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
+	register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
+	register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
+	register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	register "emmc_tx_data_cntl1" = "0x0C16"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x28162828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+	# 0:HS400(Default), 1:HS200, 2:DDR50
+	register "emmc_host_max_speed" = "2"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Proximity Sensor          |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_STANDARD
+		},
+	}"
+
+	device domain 0 on
+		device pci 00.0 on  end	# - Host Bridge
+		device pci 00.1 off end	# - DPTF
+		device pci 00.2 off end	# - NPK
+		device pci 02.0 on  end	# - Gen - Display
+		device pci 03.0 off end	# - Iunit
+		device pci 0d.0 on  end	# - P2SB
+		device pci 0d.1 off end	# - PMC
+		device pci 0d.2 on  end	# - SPI
+		device pci 0d.3 off end	# - Shared SRAM
+		device pci 0e.0 off end	# - Audio
+		device pci 11.0 on  end	# - ISH
+		device pci 12.0 on  end	# - SATA
+		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
+		device pci 13.1 on  end	# - RP 3 - PCIe A 1 - MACPHY
+		device pci 13.2 off end	# - RP 4 - PCIe-A 2
+		device pci 13.3 off end	# - RP 5 - PCIe-A 3
+		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
+		device pci 14.1 on  end	# - RP 1 - PCIe-B 1 - FPGA
+		device pci 15.0 on  end	# - XHCI
+		device pci 15.1 off end	# - XDCI
+		device pci 16.0 on	# - I2C 0
+			# Enable external RTC chip
+			chip drivers/i2c/rx6110sa
+				register "pmon_sampling" = "PMON_SAMPL_256_MS"
+				register "bks_on" = "0"
+				register "bks_off" = "1"
+				register "iocut_en" = "1"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				device i2c 0x32 on end	# RTC RX6110 SA
+			end
+		end
+		device pci 16.1 off end	# - I2C 1
+		device pci 16.2 off end	# - I2C 2
+		device pci 16.3 off end	# - I2C 3
+		device pci 17.0 off end	# - I2C 4
+		device pci 17.1 off end	# - I2C 5
+		device pci 17.2 off end	# - I2C 6
+		device pci 17.3 on  end	# - I2C 7
+		device pci 18.0 on  end	# - UART 0
+		device pci 18.1 on  end	# - UART 1
+		device pci 18.2 on  end	# - UART 2
+		device pci 18.3 on  end	# - UART 3
+		device pci 19.0 off end	# - SPI 0
+		device pci 19.1 off end	# - SPI 1
+		device pci 19.2 off end	# - SPI 2
+		device pci 1a.0 off end	# - PWM
+		device pci 1b.0 off end	# - SDCARD
+		device pci 1c.0 on  end	# - eMMC
+		device pci 1d.0 off end	# - UFS
+		device pci 1e.0 off end	# - SDIO
+		device pci 1f.0 on  end	# - LPC
+		device pci 1f.1 on  end	# - SMBUS
+	end
+end

src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c

@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <gpio.h>
+#include <hwilib.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <timer.h>
+#include <timestamp.h>
+#include <baseboard/variants.h>
+
+#define TX_DWORD3	0xa8c
+
+void variant_mainboard_final(void)
+{
+	struct device *dev = NULL;
+
+	/*
+	 * PIR6 register mapping for PCIe root ports
+	 * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
+	 */
+	pcr_write16(PID_ITSS, 0x314c, 0x0321);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
+
+	/* Enable CLKRUN_EN for power gating LPC */
+	lpc_enable_pci_clk_cntl();
+
+	/*
+	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341D bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341C bit [3:0].
+	 */
+	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+
+	/*
+	 * Correct the SATA transmit signal via the High Speed I/O Transmit
+	 * Control Register 3.
+	 * Bit [23:16] set the output voltage swing for TX line.
+	 * The value 0x4a sets the swing level to 0.58 V.
+	 */
+	pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
+}
+
+static void wait_for_legacy_dev(void *unused)
+{
+	uint32_t legacy_delay, us_since_boot;
+	struct stopwatch sw;
+
+	/* Open main hwinfo block. */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return;
+
+	/* Get legacy delay parameter from hwinfo. */
+	if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
+			      sizeof(legacy_delay)) != sizeof(legacy_delay))
+		return;
+
+	us_since_boot = get_us_since_boot();
+	/* No need to wait if the time since boot is already long enough.*/
+	if (us_since_boot > legacy_delay)
+		return;
+	stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
+	printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
+			legacy_delay - us_since_boot, legacy_delay);
+	stopwatch_wait_until_expired(&sw);
+	printk(BIOS_NOTICE, "done!\n");
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(CNV_RGI_DT, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);