GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/skolas: update dptf thermal settings 

Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast. This change is based on the discussion on
bug:235311241 comment#7.

BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Skolas system

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71692
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Sumeet Pawnikar 2023-01-25 11:44:38 +05:30 committed by Felix Held
parent c7a1084b99
commit 58c00a04d4
1 changed files with 39 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
src/mainboard/google/brya/variants/skolas/overridetree.cb
View File

@ -128,23 +128,48 @@ chip soc/intel/alderlake
## Active Policy ## Active Policy
register "policies.active" = "{ register "policies.active" = "{
[0] = { [0] = {
.target = DPTF_CPU, .target = DPTF_TEMP_SENSOR_0,
.thresholds = { .thresholds = {
TEMP_PCT(85, 90), TEMP_PCT(75, 97),
TEMP_PCT(80, 80), TEMP_PCT(70, 93),
TEMP_PCT(75, 70), TEMP_PCT(60, 86),
TEMP_PCT(70, 50), TEMP_PCT(52, 80),
TEMP_PCT(65, 30), TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 40),
} }
}, },
[1] = { [1] = {
.target = DPTF_TEMP_SENSOR_1, .target = DPTF_TEMP_SENSOR_1,
.thresholds = { .thresholds = {
TEMP_PCT(50, 90), TEMP_PCT(75, 97),
TEMP_PCT(48, 70), TEMP_PCT(70, 93),
TEMP_PCT(46, 60), TEMP_PCT(60, 86),
TEMP_PCT(43, 40), TEMP_PCT(52, 80),
TEMP_PCT(40, 30), TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 40),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(82, 97),
TEMP_PCT(78, 93),
TEMP_PCT(72, 86),
TEMP_PCT(60, 80),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(75, 97),
TEMP_PCT(70, 93),
TEMP_PCT(60, 86),
TEMP_PCT(52, 80),
TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 40),
} }
} }
}" }"
@ -152,10 +177,10 @@ chip soc/intel/alderlake
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
}" }"
## Critical Policy ## Critical Policy