soc/amd/common/data_fabric_helper: use data_fabric_get_mmio_base_size
Use data_fabric_get_mmio_base_size in data_fabric_print_mmio_conf instead of open coding the functionality. This will fix the printing of the MMIO config in the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO case which wasn't handled properly before. TEST=Console output from this function doesn't change on Mandolin: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 0 ffff 90 9 4 fed00000 fed0ffff 93 x x 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If602922648deca0caef23a9999c82acdd128b182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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@ -54,14 +54,7 @@ void data_fabric_print_mmio_conf(void)
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"idx base limit control R W NP F-ID\n");
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for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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control.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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/* Base and limit address registers don't contain the lower address bits, but
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are shifted by D18F0_MMIO_SHIFT bits */
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base = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_BASE(i))
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<< DF_MMIO_SHIFT;
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limit = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_LIMIT(i))
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<< DF_MMIO_SHIFT;
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/* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */
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limit += (1 << DF_MMIO_SHIFT) - 1;
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data_fabric_get_mmio_base_size(i, &base, &limit);
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printk(BIOS_SPEW, " %2u %16llx %16llx %8x %s %s %s %4x\n",
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i, base, limit, control.raw,
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control.re ? "x" : " ",
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