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soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE 

The previous code actually set SlpS0WithGbeSupport even when GBE is
disabled in device tree and could cause power consumption in s0ix.

This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport,
PchPmSlpS0Vm075VSupport by device tree.

SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled.

BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles

Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2019-10-22 12:51:36 +08:00 committed by Patrick Georgi
parent 61a2d25a01
commit 58e96705cb
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/cannonlake/fsp_params.c
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@ -192,6 +192,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlpResetConfig));
#endif
}
params->SlpS0WithGbeSupport = 0;
params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl;
params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport;
params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport;
/* Lan */
dev = pcidev_path_on_root(PCH_DEVFN_GBE);
@ -199,7 +203,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLanEnable = 0;
else {
params->PchLanEnable = dev->enabled;
if (config->s0ix_enable) {
if (config->s0ix_enable && params->PchLanEnable) {
/*
* The VmControl UPDs need to be set as per board
* design to allow voltage margining in S0ix to lower
* power consumption.
* But if GbE is enabled, voltage magining cannot be
* enabled, so the Vm control UPDs need to be set to 0.
*/
params->SlpS0WithGbeSupport = 1;
params->PchPmSlpS0VmRuntimeControl = 0;
params->PchPmSlpS0Vm070VSupport = 0;