lynxpoint: Kill alternative cbfs_load_payload.
With generic load using 32-bit accesses this is no longer has a huge impact it previously did. It's also unnecessarily component-speficific. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5131 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select PCIEXP_ASPM
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select SPI_FLASH
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select ALT_CBFS_LOAD_PAYLOAD
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config INTEL_LYNXPOINT_LP
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config INTEL_LYNXPOINT_LP
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bool
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bool
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@ -41,7 +41,6 @@ ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-y += watchdog.c
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ramstage-y += acpi.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += spi.c
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ramstage-y += spi.c
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@ -1,90 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 ChromeOS Authors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <arch/byteorder.h>
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#include <cbmem.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#if CONFIG_VBOOT_VERIFY_FIRMWARE
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#include <vendorcode/google/chromeos/chromeos.h>
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#else
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static inline void *vboot_get_payload(size_t *len) { return NULL; }
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#endif
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#define CACHELINE_SIZE 64
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#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1)
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#define CACHELINE_MASK (~INTRA_CACHELINE_MASK)
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/* Mirror the payload file to the default SMM location if it is small enough.
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* The default SMM region can be used since no one is using the memory at this
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* location at this stage in the boot. */
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static inline void *spi_mirror(void *file_start, int file_len)
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{
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int alignment_diff;
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char *src;
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char *dest = (void *)SMM_DEFAULT_BASE;
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alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start);
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/* Adjust file length so that the start and end points are aligned to a
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* cacheline. Coupled with the ROM caching in the CPU the SPI hardware
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* will read and cache full length cachelines. It will also prefetch
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* data as well. Once things are mirrored in memory all accesses should
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* hit the CPUs cache. */
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file_len += alignment_diff;
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file_len = ALIGN(file_len, CACHELINE_SIZE);
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printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len);
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/* Just pass back the pointer to ROM space if the file is larger
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* than the RAM mirror region. */
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if (file_len > SMM_DEFAULT_SIZE)
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return file_start;
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src = (void *)(CACHELINE_MASK & (long)file_start);
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/* Note that if mempcy is not using 32-bit moves the performance will
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* degrade because the SPI hardware prefetchers look for
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* cacheline-aligned 32-bit accesses to kick in. */
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memcpy(dest, src, file_len);
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/* Provide pointer into mirrored space. */
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return &dest[alignment_diff];
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}
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void *cbfs_load_payload(struct cbfs_media *media, const char *name)
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{
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size_t file_len;
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void *file_start;
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file_start = vboot_get_payload(&file_len);
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if (file_start != NULL)
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return spi_mirror(file_start, file_len);
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file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len);
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if (file_start == NULL)
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return NULL;
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return spi_mirror(file_start, file_len);
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}
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