lenovo/x201: Remove $PIR and MP tables.
Not sure if they ever worked. Change-Id: I77cf090763aa7ac46480a5a9583985b10b02a267 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7551 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
3c03141565
commit
5903a78e1e
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@ -10,8 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select DRIVERS_ICS_954309
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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@ -1,61 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2013 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * 16,
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0x00, (0x1f << 3) | 0x0,
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0x0000,
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0x8086, 0x3b07,
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0x00000000,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, /* u8 rfu[11] */
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0x20,/* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, { link, bitmap }, { link, bitmap }, { link, bitmap }, { link, bitmap }, slot, rfu */
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{ 0x00, (0x00 << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x03, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x01 << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, }, 0x00, 0x00 },
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{ 0x00, (0x02 << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, }, 0x00, 0x00 },
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{ 0x00, (0x16 << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x03, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x19 << 3) | 0x0, { { 0x05, 0x1cf8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1a << 3) | 0x0, { { 0x05, 0x1cf8 }, { 0x06, 0x1cf8 }, { 0x07, 0x1cf8 }, { 0x08, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1b << 3) | 0x0, { { 0x00, 0xdef8 }, { 0x02, 0x1cf8 }, { 0x00, 0xdef8 }, { 0x00, 0xdef8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1c << 3) | 0x0, { { 0x05, 0x1cf8 }, { 0x06, 0x1cf8 }, { 0x07, 0x1cf8 }, { 0x08, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1c << 3) | 0x3, { { 0x05, 0x1cf8 }, { 0x06, 0x1cf8 }, { 0x07, 0x1cf8 }, { 0x08, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1c << 3) | 0x4, { { 0x05, 0x1cf8 }, { 0x06, 0x1cf8 }, { 0x07, 0x1cf8 }, { 0x08, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1d << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x03, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1e << 3) | 0x0, { { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x03, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1f << 3) | 0x0, { { 0x08, 0x1cf8 }, { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1f << 3) | 0x2, { { 0x08, 0x1cf8 }, { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1f << 3) | 0x3, { { 0x08, 0x1cf8 }, { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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{ 0x00, (0x1f << 3) | 0x6, { { 0x08, 0x1cf8 }, { 0x01, 0x1cf8 }, { 0x02, 0x1cf8 }, { 0x04, 0x1cf8 }, }, 0x00, 0x00 },
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -1,82 +0,0 @@
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/* generated by MPTable, version 2.0.15*/
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/* as modified by RGM for coreboot */
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#define INTA 0x00
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#define INTB 0x01
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#define INTC 0x02
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#define INTD 0x03
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int isa_bus;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &isa_bus);
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, 0x2, 0x20, 0xfec00000);
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mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
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0x2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x1, 0x2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x0, 0x2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x3, 0x2, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x4, 0x2, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x5, 0x2, 0x5);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x6, 0x2, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x7, 0x2, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x8, 0x2, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0x9, 0x2, 0x9);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xa, 0x2, 0xa);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xb, 0x2, 0xb);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xc, 0x2, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xd, 0x2, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xe, 0x2, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x3, 0xf, 0x2, 0xf);
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/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_lintsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
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MP_APIC_ALL, 0x0);
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smp_write_lintsrc(mc, mp_NMI,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
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MP_APIC_ALL, 0x1);
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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