From 5913a54a3be35f4dc8e66878de443fd4c906899b Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 9 Jan 2024 16:59:37 +0100 Subject: [PATCH] soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/amd/stoneyridge/northbridge.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index bf2f992e33..2b6ba45bff 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -43,9 +43,6 @@ static void read_resources(struct device *dev) * the CPU_CLUSTER. */ mmconf_resource(dev, idx++); - - /* NB IOAPIC2 resource */ - mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); } /** @@ -301,6 +298,10 @@ void domain_read_resources(struct device *dev) /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_from_to(dev, idx++, mem_useable, tom); + /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT + code can find this resource */ + mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000); + /* If there is memory above 4GiB */ if (high_tom >> 32) { /* 4GiB -> high top usable */