Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-61
Creator: Yinghai Lu <yhlu@tyan.com> write_pirq_routing_table for x86 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
parent
80e3d96d0a
commit
59140ccdf3
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@ -23,7 +23,7 @@ struct lb_memory *write_tables(void)
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post_code(0x9a);
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post_code(0x9a);
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/* This table must be betweeen 0xf0000 & 0x100000 */
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/* This table must be betweeen 0xf0000 & 0x100000 */
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rom_table_end = copy_pirq_routing_table(rom_table_end);
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rom_table_end = write_pirq_routing_table(rom_table_end);
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rom_table_end = (rom_table_end + 1023) & ~1023;
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rom_table_end = (rom_table_end + 1023) & ~1023;
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/* copy the smp block to address 0 */
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/* copy the smp block to address 0 */
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@ -41,8 +41,10 @@ extern const struct irq_routing_table intel_irq_routing_table;
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#if HAVE_PIRQ_TABLE==1
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#if HAVE_PIRQ_TABLE==1
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unsigned long copy_pirq_routing_table(unsigned long start);
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unsigned long copy_pirq_routing_table(unsigned long start);
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unsigned long write_pirq_routing_table(unsigned long start);
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#else
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#else
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#define copy_pirq_routing_table(start) (start)
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#define copy_pirq_routing_table(start) (start)
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#define write_pirq_routing_table(start) (start)
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#endif
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#endif
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#endif /* ARCH_PIRQ_ROUTING_H */
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#endif /* ARCH_PIRQ_ROUTING_H */
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@ -35,3 +35,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -50,3 +50,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
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IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -32,3 +32,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -55,3 +55,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -52,3 +52,8 @@ const struct irq_routing_table intel_irq_routing_table = {
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -42,3 +42,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
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IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -28,3 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x00,(0x02<<3)|0x0, {{0x59, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00,(0x02<<3)|0x0, {{0x59, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -30,3 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -30,3 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -25,3 +25,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
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{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -30,3 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -55,3 +55,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -54,3 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
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IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -32,3 +32,8 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -26,3 +26,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -38,3 +38,8 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x03,(0x05<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x6, 0x0},
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{0x03,(0x05<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x6, 0x0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -34,3 +34,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x2,(0x0c<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x2,(0x0c<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -35,3 +35,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x3,(0x0b<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0, 0}}, 0, 0},
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{0x3,(0x0b<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0, 0}}, 0, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -35,3 +35,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
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{0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -31,3 +31,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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{0x4,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x4,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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}
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}
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};
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -4,36 +4,298 @@
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <arch/pirq_routing.h>
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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PIRQ_VERSION, /* u16 version */
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32+16*15, /* there can be total 15 devices on the bus */
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32+16*15, /* there can be total 15 devices on the bus */
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1, /* Where the interrupt router lies (bus) */
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1, /* Where the interrupt router lies (bus) */
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(4<<3)|3, /* Where the interrupt router lies (dev) */
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(4<<3)|3, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu
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{
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re (including checksum) */
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{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{
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{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||||
{0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
{0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
{0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
{0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0},
|
{0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
{0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
{0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0},
|
||||||
{0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
{0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
{0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
{0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||||
}
|
{0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
||||||
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
unsigned reg;
|
||||||
|
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||||
|
if (!dev) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||||
|
uint32_t config_map;
|
||||||
|
unsigned dst_node;
|
||||||
|
unsigned dst_link;
|
||||||
|
unsigned bus_base;
|
||||||
|
config_map = pci_read_config32(dev, reg);
|
||||||
|
if ((config_map & 3) != 3) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
dst_node = (config_map >> 4) & 7;
|
||||||
|
dst_link = (config_map >> 8) & 3;
|
||||||
|
bus_base = (config_map >> 16) & 0xff;
|
||||||
|
#if 0
|
||||||
|
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||||
|
dst_node, dst_link, bus_base,
|
||||||
|
reg, config_map);
|
||||||
|
#endif
|
||||||
|
if ((dst_node == node) && (dst_link == link))
|
||||||
|
{
|
||||||
|
return bus_base;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||||
|
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||||
|
uint8_t slot, uint8_t rfu)
|
||||||
|
{
|
||||||
|
pirq_info->bus = bus;
|
||||||
|
pirq_info->devfn = devfn;
|
||||||
|
pirq_info->irq[0].link = link0;
|
||||||
|
pirq_info->irq[0].bitmap = bitmap0;
|
||||||
|
pirq_info->irq[1].link = link1;
|
||||||
|
pirq_info->irq[1].bitmap = bitmap1;
|
||||||
|
pirq_info->irq[2].link = link2;
|
||||||
|
pirq_info->irq[2].bitmap = bitmap2;
|
||||||
|
pirq_info->irq[3].link = link3;
|
||||||
|
pirq_info->irq[3].bitmap = bitmap3;
|
||||||
|
pirq_info->slot = slot;
|
||||||
|
pirq_info->rfu = rfu;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct irq_routing_table *pirq;
|
||||||
|
struct irq_info *pirq_info;
|
||||||
|
unsigned slot_num;
|
||||||
|
uint8_t *v;
|
||||||
|
|
||||||
|
uint8_t sum=0;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
unsigned char bus_chain_0;
|
||||||
|
unsigned char bus_8131_1;
|
||||||
|
unsigned char bus_8131_2;
|
||||||
|
unsigned char bus_8111_1;
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
|
||||||
|
/* HT chain 0 */
|
||||||
|
bus_chain_0 = node_link_to_bus(0, 0);
|
||||||
|
if (bus_chain_0 == 0) {
|
||||||
|
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||||
|
bus_chain_0 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 8111 */
|
||||||
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8111_1 = 4;
|
||||||
|
}
|
||||||
|
/* 8131-1 */
|
||||||
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_1 = 2;
|
||||||
|
}
|
||||||
|
/* 8131-2 */
|
||||||
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_2 = 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Align the table to be 16 byte aligned. */
|
||||||
|
addr += 15;
|
||||||
|
addr &= ~15;
|
||||||
|
|
||||||
|
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||||
|
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||||
|
|
||||||
|
pirq = (void *)(addr);
|
||||||
|
v = (uint8_t *)(addr);
|
||||||
|
|
||||||
|
pirq->signature = PIRQ_SIGNATURE;
|
||||||
|
pirq->version = PIRQ_VERSION;
|
||||||
|
|
||||||
|
pirq->rtr_bus = bus_chain_0;
|
||||||
|
pirq->rtr_devfn = (4<<3)|3;
|
||||||
|
|
||||||
|
pirq->exclusive_irqs = 0;
|
||||||
|
|
||||||
|
pirq->rtr_vendor = 0x1022;
|
||||||
|
pirq->rtr_device = 0x746b;
|
||||||
|
|
||||||
|
pirq->miniport_data = 0;
|
||||||
|
|
||||||
|
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||||
|
|
||||||
|
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||||
|
slot_num = 0;
|
||||||
|
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3));
|
||||||
|
if (dev) {
|
||||||
|
/* initialize PCI interupts - these assignments depend
|
||||||
|
on the PCB routing of PINTA-D
|
||||||
|
|
||||||
|
PINTA = IRQ5
|
||||||
|
PINTB = IRQ9
|
||||||
|
PINTC = IRQ11
|
||||||
|
PINTD = IRQ10
|
||||||
|
*/
|
||||||
|
pci_write_config16(dev, 0x56, 0xab95);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
printk_info("setting Onboard AMD Southbridge \n");
|
||||||
|
static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
|
||||||
|
pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
|
||||||
|
write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Onboard AMD USB \n");
|
||||||
|
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
|
||||||
|
pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
|
||||||
|
write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Onboard ATI Display Adapter\n");
|
||||||
|
static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
|
||||||
|
pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
|
||||||
|
write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Slot 1\n");
|
||||||
|
static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
|
||||||
|
pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Slot 2\n");
|
||||||
|
static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
|
||||||
|
pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Slot 3\n");
|
||||||
|
static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
|
||||||
|
pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Slot 4\n");
|
||||||
|
static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
|
||||||
|
pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Slot 5 \n");
|
||||||
|
static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
|
||||||
|
pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
|
||||||
|
write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Onboard SI Serail ATA\n");
|
||||||
|
static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
|
||||||
|
pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
|
||||||
|
write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Onboard Intel NIC\n");
|
||||||
|
static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
|
||||||
|
pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
|
||||||
|
write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
printk_info("setting Onboard Adaptec SCSI\n");
|
||||||
|
static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
|
||||||
|
pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#if 0
|
||||||
|
//??
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
printk_info("setting Onboard Broadcom NIC\n");
|
||||||
|
static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
|
||||||
|
pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#if 0
|
||||||
|
//?? what's this?
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
//?? what's this?
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
pirq->size = 32 + 16 * slot_num;
|
||||||
|
|
||||||
|
for (i = 0; i < pirq->size; i++)
|
||||||
|
sum += v[i];
|
||||||
|
|
||||||
|
sum = pirq->checksum - sum;
|
||||||
|
|
||||||
|
if (sum != pirq->checksum) {
|
||||||
|
pirq->checksum = sum;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (unsigned long) pirq_info;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -8,7 +8,40 @@
|
||||||
#include <cpu/amd/dualcore.h>
|
#include <cpu/amd/dualcore.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define ASSIGN_IRQ 0
|
|
||||||
|
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
unsigned reg;
|
||||||
|
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||||
|
if (!dev) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||||
|
uint32_t config_map;
|
||||||
|
unsigned dst_node;
|
||||||
|
unsigned dst_link;
|
||||||
|
unsigned bus_base;
|
||||||
|
config_map = pci_read_config32(dev, reg);
|
||||||
|
if ((config_map & 3) != 3) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
dst_node = (config_map >> 4) & 7;
|
||||||
|
dst_link = (config_map >> 8) & 3;
|
||||||
|
bus_base = (config_map >> 16) & 0xff;
|
||||||
|
#if 0
|
||||||
|
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||||
|
dst_node, dst_link, bus_base,
|
||||||
|
reg, config_map);
|
||||||
|
#endif
|
||||||
|
if ((dst_node == node) && (dst_link == link))
|
||||||
|
{
|
||||||
|
return bus_base;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
void *smp_write_config_table(void *v)
|
void *smp_write_config_table(void *v)
|
||||||
{
|
{
|
||||||
|
|
@ -19,6 +52,7 @@ void *smp_write_config_table(void *v)
|
||||||
|
|
||||||
unsigned char bus_num;
|
unsigned char bus_num;
|
||||||
unsigned char bus_isa;
|
unsigned char bus_isa;
|
||||||
|
unsigned char bus_chain_0;
|
||||||
unsigned char bus_8131_1;
|
unsigned char bus_8131_1;
|
||||||
unsigned char bus_8131_2;
|
unsigned char bus_8131_2;
|
||||||
unsigned char bus_8111_1;
|
unsigned char bus_8111_1;
|
||||||
|
|
@ -48,8 +82,15 @@ void *smp_write_config_table(void *v)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
|
|
||||||
|
/* HT chain 0 */
|
||||||
|
bus_chain_0 = node_link_to_bus(0, 0);
|
||||||
|
if (bus_chain_0 == 0) {
|
||||||
|
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||||
|
bus_chain_0 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
/* 8111 */
|
/* 8111 */
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
|
@ -62,7 +103,7 @@ void *smp_write_config_table(void *v)
|
||||||
bus_isa = 5;
|
bus_isa = 5;
|
||||||
}
|
}
|
||||||
/* 8131-1 */
|
/* 8131-1 */
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
|
@ -73,7 +114,7 @@ void *smp_write_config_table(void *v)
|
||||||
bus_8131_1 = 2;
|
bus_8131_1 = 2;
|
||||||
}
|
}
|
||||||
/* 8131-2 */
|
/* 8131-2 */
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
|
@ -106,14 +147,14 @@ void *smp_write_config_table(void *v)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||||
if (res) {
|
if (res) {
|
||||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
|
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||||
if (res) {
|
if (res) {
|
||||||
|
|
@ -137,50 +178,16 @@ void *smp_write_config_table(void *v)
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, apicid_8111, 0x13);
|
|
||||||
|
|
||||||
{
|
|
||||||
device_t dev;
|
|
||||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x746b, 0);
|
|
||||||
if (dev) {
|
|
||||||
/* initialize PCI interupts - these assignments depend
|
|
||||||
on the PCB routing of PINTA-D
|
|
||||||
|
|
||||||
PINTA = IRQ5
|
|
||||||
PINTB = IRQ9
|
|
||||||
PINTC = IRQ11
|
|
||||||
PINTD = IRQ10
|
|
||||||
*/
|
|
||||||
pci_write_config16(dev, 0x56, 0xab95);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard AMD Southbridge \n");
|
|
||||||
static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
|
|
||||||
pci_assign_irqs(1, 4, slotIrqs_1_4);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//On Board AMD USB
|
//On Board AMD USB
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard AMD USB \n");
|
|
||||||
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
|
|
||||||
pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//On Board ATI Display Adapter
|
//On Board ATI Display Adapter
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard ATI Display Adapter\n");
|
|
||||||
static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
|
|
||||||
pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
//Slot 5 PCI 32
|
//Slot 5 PCI 32
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
|
||||||
|
|
@ -188,31 +195,13 @@ void *smp_write_config_table(void *v)
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Slot 5 \n");
|
|
||||||
static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
|
|
||||||
pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
//Onboard SI Serial ATA
|
//Onboard SI Serial ATA
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard SI Serail ATA\n");
|
|
||||||
static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
|
|
||||||
pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//Onboard Intel 82551 10/100M NIC
|
//Onboard Intel 82551 10/100M NIC
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard Intel NIC\n");
|
|
||||||
static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
|
|
||||||
pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
//Slot 3 PCIX 100/66
|
//Slot 3 PCIX 100/66
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
|
||||||
|
|
@ -220,46 +209,23 @@ void *smp_write_config_table(void *v)
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Slot 3\n");
|
|
||||||
static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
|
|
||||||
pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//Slot 4 PCIX 100/66
|
//Slot 4 PCIX 100/66
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Slot 4\n");
|
|
||||||
static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
|
|
||||||
pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
//Onboard adaptec scsi
|
//Onboard adaptec scsi
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard Adaptec SCSI\n");
|
|
||||||
static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
|
|
||||||
pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//On Board NIC
|
//On Board NIC
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
|
||||||
|
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Onboard Broadcom NIC\n");
|
|
||||||
static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
|
|
||||||
pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
//Slot 1 PCI-X 133/100/66
|
//Slot 1 PCI-X 133/100/66
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
|
||||||
|
|
@ -267,24 +233,12 @@ void *smp_write_config_table(void *v)
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Slot 1\n");
|
|
||||||
static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
|
|
||||||
pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//Slot 2 PCI-X 133/100/66
|
//Slot 2 PCI-X 133/100/66
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
|
||||||
|
|
||||||
#if ASSIGN_IRQ
|
|
||||||
printk_info("setting Slot 2\n");
|
|
||||||
static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
|
|
||||||
pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||||
|
|
|
||||||
|
|
@ -33,3 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -33,3 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -33,3 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,10 @@
|
||||||
|
|
||||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||||
*/
|
*/
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
#include <arch/pirq_routing.h>
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
const struct irq_routing_table intel_irq_routing_table = {
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
|
@ -27,7 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||||
{0x4,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
{0x4,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||||
{0x7,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
|
{0x7,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
|
||||||
{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
{0x8,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||||
|
|
@ -37,3 +40,369 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
unsigned reg;
|
||||||
|
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||||
|
if (!dev) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||||
|
uint32_t config_map;
|
||||||
|
unsigned dst_node;
|
||||||
|
unsigned dst_link;
|
||||||
|
unsigned bus_base;
|
||||||
|
config_map = pci_read_config32(dev, reg);
|
||||||
|
if ((config_map & 3) != 3) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
dst_node = (config_map >> 4) & 7;
|
||||||
|
dst_link = (config_map >> 8) & 3;
|
||||||
|
bus_base = (config_map >> 16) & 0xff;
|
||||||
|
#if 0
|
||||||
|
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||||
|
dst_node, dst_link, bus_base,
|
||||||
|
reg, config_map);
|
||||||
|
#endif
|
||||||
|
if ((dst_node == node) && (dst_link == link))
|
||||||
|
{
|
||||||
|
return bus_base;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||||
|
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||||
|
uint8_t slot, uint8_t rfu)
|
||||||
|
{
|
||||||
|
pirq_info->bus = bus;
|
||||||
|
pirq_info->devfn = devfn;
|
||||||
|
pirq_info->irq[0].link = link0;
|
||||||
|
pirq_info->irq[0].bitmap = bitmap0;
|
||||||
|
pirq_info->irq[1].link = link1;
|
||||||
|
pirq_info->irq[1].bitmap = bitmap1;
|
||||||
|
pirq_info->irq[2].link = link2;
|
||||||
|
pirq_info->irq[2].bitmap = bitmap2;
|
||||||
|
pirq_info->irq[3].link = link3;
|
||||||
|
pirq_info->irq[3].bitmap = bitmap3;
|
||||||
|
pirq_info->slot = slot;
|
||||||
|
pirq_info->rfu = rfu;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct irq_routing_table *pirq;
|
||||||
|
struct irq_info *pirq_info;
|
||||||
|
unsigned slot_num;
|
||||||
|
uint8_t *v;
|
||||||
|
|
||||||
|
uint8_t sum=0;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
unsigned char bus_ck804_0; //1
|
||||||
|
unsigned char bus_ck804_1; //2
|
||||||
|
unsigned char bus_ck804_2; //3
|
||||||
|
unsigned char bus_ck804_3; //4
|
||||||
|
unsigned char bus_ck804_4; //5
|
||||||
|
unsigned char bus_ck804_5; //6
|
||||||
|
unsigned char bus_8131_0; //7
|
||||||
|
unsigned char bus_8131_1; //8
|
||||||
|
unsigned char bus_8131_2; //9
|
||||||
|
unsigned char bus_ck804b_0;//a
|
||||||
|
unsigned char bus_ck804b_1;//b
|
||||||
|
unsigned char bus_ck804b_2;//c
|
||||||
|
unsigned char bus_ck804b_3;//d
|
||||||
|
unsigned char bus_ck804b_4;//e
|
||||||
|
unsigned char bus_ck804b_5;//f
|
||||||
|
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
|
||||||
|
|
||||||
|
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||||
|
if (bus_ck804_0 == 0) {
|
||||||
|
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||||
|
bus_ck804_0 = 1;
|
||||||
|
}
|
||||||
|
/* CK804 */
|
||||||
|
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
#if 0
|
||||||
|
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804_2++;
|
||||||
|
#else
|
||||||
|
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804_5++;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||||
|
|
||||||
|
bus_ck804_1 = 2;
|
||||||
|
#if 0
|
||||||
|
bus_ck804_2 = 3;
|
||||||
|
#else
|
||||||
|
bus_ck804_5 = 3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
#if 0
|
||||||
|
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804_3++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||||
|
|
||||||
|
bus_ck804_3 = bus_ck804_2+1;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804_4++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||||
|
|
||||||
|
bus_ck804_4 = bus_ck804_3+1;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804_5++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||||
|
|
||||||
|
bus_ck804_5 = bus_ck804_4+1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_8131_0++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||||
|
|
||||||
|
bus_8131_0 = bus_ck804_5+1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 8131-1 */
|
||||||
|
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_8131_2++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||||
|
|
||||||
|
bus_8131_1 = bus_8131_0+1;
|
||||||
|
bus_8131_2 = bus_8131_0+2;
|
||||||
|
}
|
||||||
|
/* 8131-2 */
|
||||||
|
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804b_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804b_0++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||||
|
|
||||||
|
bus_8131_2 = bus_8131_1+1;
|
||||||
|
bus_ck804b_0 = bus_8131_1+2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* CK804b */
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804b_2++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09);
|
||||||
|
|
||||||
|
bus_ck804b_1 = bus_ck804b_0+1;
|
||||||
|
bus_ck804b_2 = bus_ck804b_0+2;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804b_3++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b);
|
||||||
|
|
||||||
|
bus_ck804b_2 = bus_ck804b_0+1;
|
||||||
|
bus_ck804b_3 = bus_ck804b_0+2;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804b_4++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c);
|
||||||
|
|
||||||
|
bus_ck804b_4 = bus_ck804b_3+1;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_ck804b_5++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d);
|
||||||
|
|
||||||
|
bus_ck804b_5 = bus_ck804b_4+1;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0e);
|
||||||
|
#if 1
|
||||||
|
bus_ck804b_5 = bus_ck804b_0+1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Align the table to be 16 byte aligned. */
|
||||||
|
addr += 15;
|
||||||
|
addr &= ~15;
|
||||||
|
|
||||||
|
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||||
|
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||||
|
|
||||||
|
pirq = (void *)(addr);
|
||||||
|
v = (uint8_t *)(addr);
|
||||||
|
|
||||||
|
pirq->signature = PIRQ_SIGNATURE;
|
||||||
|
pirq->version = PIRQ_VERSION;
|
||||||
|
|
||||||
|
pirq->rtr_bus = bus_ck804_0;
|
||||||
|
pirq->rtr_devfn = ((CK804_DEVN_BASE+9)<<3)|0;
|
||||||
|
|
||||||
|
pirq->exclusive_irqs = 0;
|
||||||
|
|
||||||
|
pirq->rtr_vendor = 0x10de;
|
||||||
|
pirq->rtr_device = 0x005c;
|
||||||
|
|
||||||
|
pirq->miniport_data = 0;
|
||||||
|
|
||||||
|
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||||
|
|
||||||
|
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||||
|
slot_num = 0;
|
||||||
|
//pci bridge
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//pcix bridge
|
||||||
|
write_pirq_info(pirq_info, bus_8131_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//second pci beidge
|
||||||
|
write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#if 0
|
||||||
|
//smbus
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//usb
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//audio
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//sata
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//sata
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//nic
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//Slot1 PCIE x16
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//firewire
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//Slot2 pci
|
||||||
|
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//nic
|
||||||
|
write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
//Slot3 PCIE x16
|
||||||
|
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//Slot4 PCIX
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//Slot5 PCIX
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//onboard scsi
|
||||||
|
write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
|
||||||
|
//Slot6 PCIX
|
||||||
|
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||||
|
pirq_info++; slot_num++;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
pirq->size = 32 + 16 * slot_num;
|
||||||
|
|
||||||
|
for (i = 0; i < pirq->size; i++)
|
||||||
|
sum += v[i];
|
||||||
|
|
||||||
|
sum = pirq->checksum - sum;
|
||||||
|
|
||||||
|
if (sum != pirq->checksum) {
|
||||||
|
pirq->checksum = sum;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (unsigned long) pirq_info;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -44,3 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -44,3 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -28,3 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -30,3 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
||||||
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
|
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue