soc/intel/tigerlake: Configure ClkReq according to mainboard design
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -60,12 +60,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PcieClkSrcUsage[i] = 0xff;
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}
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memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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sizeof(config->PcieClkSrcClkReq));
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m_cfg->PrmrrSize = config->PrmrrSize;
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m_cfg->EnableC6Dram = config->enable_c6dram;
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/* Disable BIOS Guard */
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m_cfg->BiosGuard = 0;
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/* UART Debug Log*/
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/* UART Debug Log */
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m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
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DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
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m_cfg->PcdIsaSerialUartBase = 0x0;
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