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soc/intel/tigerlake: Configure ClkReq according to mainboard design 

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-01-08 11:51:37 -08:00 committed by Patrick Georgi
parent 6d126acfac
commit 591b0ff535
1 changed files with 4 additions and 1 deletions
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3
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
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@ -60,6 +60,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PcieClkSrcUsage[i] = 0xff; m_cfg->PcieClkSrcUsage[i] = 0xff;
} }
memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->EnableC6Dram = config->enable_c6dram; m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */ /* Disable BIOS Guard */