Move the CPU specific includes from
src/arch/i386/Makefile.inc to the respective CPU directories. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -117,61 +117,17 @@ ldscripts += $(src)/arch/i386/lib/id.lds
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endif
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crt0s += $(src)/cpu/x86/fpu_enable.inc
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ifeq ($(CONFIG_CPU_AMD_GX1),y)
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crt0s += $(src)/cpu/amd/model_gx1/cpu_setup.inc
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crt0s += $(src)/cpu/amd/model_gx1/gx_setup.inc
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endif
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ifeq ($(CONFIG_SSE),y)
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crt0s += $(src)/cpu/x86/sse_enable.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_LX),y)
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crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_F),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_F_1207),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2R2),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_S1G1),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_754),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_939),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_AMD_SOCKET_940),y)
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crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_INTEL_ATOM_230),y)
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crt0s += $(src)/cpu/intel/model_106cx/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_INTEL_CORE),y)
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crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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endif
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y)
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crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y)
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crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_CPU_VIA_C7),y)
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crt0s += $(src)/cpu/via/car/cache_as_ram.inc
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endif
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# who else could use this?
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crt0s += $(cpu_incs)
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#
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# FIXME move to CPU_INTEL_SOCKET_MPGA604
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#
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ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
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crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
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ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds
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endif
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ifeq ($(CONFIG_LLSHELL),y)
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@ -23,3 +23,6 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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driver-y += model_gx1_init.o
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cpu_incs += $(src)/cpu/amd/model_gx1/cpu_setup.inc
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cpu_incs += $(src)/cpu/amd/model_gx1/gx_setup.inc
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@ -6,3 +6,5 @@ subdirs-y += ../../x86/smm
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driver-y += model_lx_init.o
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obj-y += cpubug.o
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obj-y += vsmsetup.o
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cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
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@ -8,3 +8,5 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -8,3 +8,5 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -8,3 +8,5 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -9,3 +9,5 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -9,3 +9,5 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../../x86/mtrr
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -9,3 +9,5 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -9,3 +9,5 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,3 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../../x86/mtrr
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -8,3 +8,5 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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@ -1 +1,3 @@
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driver-y += model_106cx_init.o
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cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc
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@ -1 +1,3 @@
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driver-y += model_6ex_init.o
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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@ -6,3 +6,5 @@ subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/x86/car/cache_as_ram.inc
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@ -6,3 +6,5 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../../intel/microcode
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driver-y += model_c7_init.o
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cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
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@ -1,29 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Stefan Reinauer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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SECTIONS {
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.init . : {
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_init = .;
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*(.init.text);
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*(.init.rodata);
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*(.init.rodata.*);
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. = ALIGN(16);
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_einit = .;
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}
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}
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