440BX: Do not hardcode DIMM number + size anymore.
The code currently assumes a 4-DIMM-slots board, this will be fixed soon. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -32,11 +32,27 @@
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* Any addresses between 0x00 and 0xff not listed below are either
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* Reserved or Intel Reserved and should not be touched.
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*/
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#define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
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#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */
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#define DRAMT 0x58 /* DRAM Timing (0x03). */
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#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */
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#define PAM0 0x59
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#define PAM1 0x5a
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#define PAM2 0x5b
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#define PAM3 0x5c
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#define PAM4 0x5d
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#define PAM5 0x5e
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#define PAM6 0x5f
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#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */
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#define DRB0 0x60
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#define DRB1 0x61
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#define DRB2 0x62
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#define DRB3 0x63
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#define DRB4 0x64
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#define DRB5 0x65
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#define DRB6 0x66
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#define DRB7 0x67
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#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */
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#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */
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#define SMRAM 0x72 /* System Management RAM Control (0x02). */
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@ -50,27 +66,24 @@
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#define ERRCMD 0x90 /* Error Command Register (0x80). */
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#define ERRSTS 0x91 /* Error Status (0x0000). */
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// TODO: AGP stuff.
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#define ACAPID 0xa0 /* AGP Capability Identifier (0x00100002 or 0x00000000) */
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#define AGPSTAT 0xa4 /* AGP Status Register (0x1f000203, read only) */
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#define AGPCMD 0xa8 /* AGP Command Register (0x00000000) */
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#define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */
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#define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */
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#define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */
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#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */
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#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */
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#define BSPAD0 0xd0 /* These are free for our use. */
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#define BSPAD1 0xd1
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#define BSPAD2 0xd2
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#define BSPAD3 0xd3
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#define BSPAD4 0xd4
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#define BSPAD5 0xd5
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#define BSPAD6 0xd6
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#define BSPAD7 0xd7
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#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
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#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
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#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */
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/* For convenience: */
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#define DRB0 0x60
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#define DRB1 0x61
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#define DRB2 0x62
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#define DRB3 0x63
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#define DRB4 0x64
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#define DRB5 0x65
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#define DRB6 0x66
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#define DRB7 0x67
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#define PAM0 0x59
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#define PAM1 0x5a
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#define PAM2 0x5b
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#define PAM3 0x5c
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#define PAM4 0x5d
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#define PAM5 0x5e
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#define PAM6 0x5f
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,6 +24,7 @@
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#include <delay.h>
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#include <stdlib.h>
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#include "i440bx.h"
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#include "raminit.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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@ -185,14 +187,23 @@ static const long register_values[] = {
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* 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
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* 11 = Read/Write (all access goes to DRAM)
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*/
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// TODO
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PAM0, 0x00, 0x00,
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PAM1, 0x00, 0x00,
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PAM2, 0x00, 0x00,
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PAM3, 0x00, 0x00,
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PAM4, 0x00, 0x00,
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PAM5, 0x00, 0x00,
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PAM6, 0x00, 0x00,
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/*
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* Map all legacy regions to RAM (read/write). This is required if
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* you want to use the RAM area from 768 KB - 1 MB. If the PAM
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* registers are not set here appropriately, the RAM in that region
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* will not be accessible, thus a RAM check of it will also fail.
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*
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* TODO: This was set in sdram_set_spd_registers().
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* Test if it still works when set here.
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*/
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PAM0, 0x00, 0x30,
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PAM1, 0x00, 0x33,
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PAM2, 0x00, 0x33,
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PAM3, 0x00, 0x33,
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PAM4, 0x00, 0x33,
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PAM5, 0x00, 0x33,
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PAM6, 0x00, 0x33,
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/* DRB[0:7] - DRAM Row Boundary Registers
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* 0x60 - 0x67
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@ -340,6 +351,9 @@ static const long register_values[] = {
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// PMCR, 0x00, 0x14,
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// PMCR, 0x00, 0x10,
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PMCR, 0x00, 0x00,
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/* Enable SCRR.SRRAEN and let BX choose the SRR. */
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SCRR + 1, 0x00, 0x10,
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};
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/*-----------------------------------------------------------------------------
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@ -374,8 +388,8 @@ static void do_ram_command(u32 command)
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/* Send the RAM command to each row of memory. */
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dimm_start = 0;
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for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
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addr_offset = 0;
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caslatency = 3; /* TODO: Dynamically get CAS latency later. */
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addr_offset = 0;
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caslatency = 3; /* TODO: Dynamically get CAS latency later. */
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if (command == RAM_COMMAND_MRS) {
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/*
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* MAA[12:11,9:0] must be inverted when sent to DIMM
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@ -411,6 +425,19 @@ static void do_ram_command(u32 command)
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}
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}
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static void set_dram_buffer_strength(void)
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{
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/* TODO: This needs to be set according to the DRAM tech
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* (x8, x16, or x32). Argh, Intel provides no docs on this!
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* Currently, it needs to be pulled from the output of
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* lspci -xxx Rx92
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*
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* Relevant registers: MBSC, MBFS, BUFFC.
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*/
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pci_write_config8(NB, MBSC, 0x03);
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}
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/*-----------------------------------------------------------------------------
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DIMM-independant configuration functions.
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-----------------------------------------------------------------------------*/
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@ -458,69 +485,311 @@ static void sdram_set_registers(void)
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reg &= register_values[i + 1];
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reg |= register_values[i + 2] & ~(register_values[i + 1]);
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pci_write_config8(NB, register_values[i], reg);
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#if 0
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PRINT_DEBUG(" Set register 0x");
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PRINT_DEBUG_HEX8(register_values[i]);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX8(reg);
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PRINT_DEBUG("\r\n");
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#endif
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}
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}
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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};
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static struct dimm_size spd_get_dimm_size(unsigned int device)
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{
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struct dimm_size sz;
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int i, module_density, dimm_banks;
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sz.side1 = 0;
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module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
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dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
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/* Find the size of side1. */
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/* Find the larger value. The larger value is always side1. */
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for (i = 512; i >= 0; i >>= 1) {
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if ((module_density & i) == i) {
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sz.side1 = i;
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break;
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}
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}
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/* Set to 0 in case it's single sided. */
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sz.side2 = 0;
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/* Test if it's a dual-sided DIMM. */
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if (dimm_banks > 1) {
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/* Test if there's a second value. If so it's asymmetrical. */
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if (module_density != i) {
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/*
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* Find second value, picking up where we left off.
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* i >>= 1 done initially to make sure we don't get
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* the same value again.
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*/
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for (i >>= 1; i >= 0; i >>= 1) {
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if (module_density == (sz.side1 | i)) {
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sz.side2 = i;
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break;
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}
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}
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/* If not, it's symmetrical. */
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} else {
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sz.side2 = sz.side1;
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}
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}
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/*
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* SPD byte 31 is the memory size divided by 4 so we
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* need to muliply by 4 to get the total size.
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*/
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sz.side1 *= 4;
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sz.side2 *= 4;
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return sz;
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}
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/*
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* Sets DRAM attributes one DIMM at a time, based on SPD data.
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* Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC.
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*/
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static void set_dram_row_attributes(void)
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{
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int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc;
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u8 bpr; /* Top 8 bits of PGPOL */
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edosd = 0;
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rps = 0;
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drb = 0;
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bpr = 0;
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nbxecc = 0xff;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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unsigned int device;
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device = DIMM_SPD_BASE + i;
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bpr >>= 2;
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/* First check if a DIMM is actually present. */
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value = spd_read_byte(device, SPD_MEMORY_TYPE);
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/* This is 440BX! We do EDO too! */
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if (value == SPD_MEMORY_TYPE_EDO
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|| value == SPD_MEMORY_TYPE_SDRAM) {
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PRINT_DEBUG("Found ");
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if (value == SPD_MEMORY_TYPE_EDO) {
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edosd |= 0x02;
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} else if (value == SPD_MEMORY_TYPE_SDRAM) {
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edosd |= 0x04;
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}
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PRINT_DEBUG("DIMM in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\r\n");
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if (edosd == 0x06) {
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print_err("Mixing EDO/SDRAM unsupported!\r\n");
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die("HALT\r\n");
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}
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/* "DRA" is our RPS for the two rows on this DIMM. */
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dra = 0;
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/* Columns */
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col = spd_read_byte(device, SPD_NUM_COLUMNS);
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/*
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* Is this an ECC DIMM? Actually will be a 2 if so.
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* TODO: Other register than NBXCFG also needs this
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* ECC information.
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*/
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ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
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/* Data width */
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width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
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/* Exclude error checking data width from page size calculations */
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if (ecc) {
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value = spd_read_byte(device,
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SPD_ERROR_CHECKING_SDRAM_WIDTH);
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width -= value;
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/* ### ECC */
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/* Clear top 2 bits to help set up NBXCFG. */
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ecc &= 0x3f;
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} else {
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/* Without ECC, top 2 bits should be 11. */
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ecc |= 0xc0;
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}
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/* Calculate page size in bits. */
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value = ((1 << col) * width);
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/* Convert to KB. */
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dra = (value >> 13);
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/* Number of banks of DIMM (single or double sided). */
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value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
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/* Once we have dra, col is done and can be reused.
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* So it's reused for number of banks.
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*/
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col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
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if (value == 1) {
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/*
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* Second bank of 1-bank DIMMs "doesn't have
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* ECC" - or anything.
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*/
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ecc |= 0x80;
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if (dra == 2) {
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dra = 0x0; /* 2KB */
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} else if (dra == 4) {
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dra = 0x1; /* 4KB */
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} else if (dra == 8) {
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dra = 0x2; /* 8KB */
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} else {
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dra = -1;
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}
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/*
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* Sets a flag in PGPOL[BPR] if this DIMM has
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* 4 banks per row.
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*/
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if (col == 4)
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bpr |= 0x40;
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} else if (value == 2) {
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if (dra == 2) {
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dra = 0x0; /* 2KB */
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} else if (dra == 4) {
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dra = 0x05; /* 4KB */
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} else if (dra == 8) {
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dra = 0x0a; /* 8KB */
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} else {
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dra = -1;
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}
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/* Ditto */
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if (col == 4)
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bpr |= 0xc0;
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} else {
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print_err("# of banks of DIMM unsupported!\r\n");
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die("HALT\r\n");
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}
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if (dra == -1) {
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print_err("Page size not supported\r\n");
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die("HALT\r\n");
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}
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/*
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* 440BX supports asymmetrical dual-sided DIMMs,
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* but can't handle DIMMs smaller than 8MB per
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* side or larger than 128MB per side.
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*/
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struct dimm_size sz = spd_get_dimm_size(device);
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if ((sz.side1 < 8)) {
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print_err("DIMMs smaller than 8MB per side\r\n"
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"are not supported on this NB.\r\n");
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die("HALT\r\n");
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}
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if ((sz.side1 > 128)) {
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print_err ("DIMMs > 128MB per side\r\n"
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"are not supported on this NB\r\n");
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die("HALT\r\n");
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}
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/* Divide size by 8 to set up the DRB registers. */
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drb += (sz.side1 / 8);
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/*
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* Build the DRB for the next row in MSB so it gets
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* placed in DRB[n+1] where it belongs when written
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* as a 16-bit word.
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*/
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drb &= 0xff;
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drb |= (drb + (sz.side2 / 8)) << 8;
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} else {
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#if 0
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PRINT_DEBUG("No DIMM found in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\r\n");
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#endif
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/* If there's no DIMM in the slot, set dra to 0x00. */
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dra = 0x00;
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ecc = 0xc0;
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/* Still have to propagate DRB over. */
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drb &= 0xff;
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drb |= (drb << 8);
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}
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pci_write_config16(NB, DRB + (2 * i), drb);
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#if 0
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PRINT_DEBUG("DRB has been set to 0x");
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PRINT_DEBUG_HEX16(drb);
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PRINT_DEBUG("\r\n");
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#endif
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/* Brings the upper DRB back down to be base for
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* DRB calculations for the next two rows.
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*/
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drb >>= 8;
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rps |= (dra & 0x0f) << (i * 4);
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nbxecc = (nbxecc >> 2) | (ecc & 0xc0);
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}
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/* Set paging policy register. */
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pci_write_config8(NB, PGPOL + 1, bpr);
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PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
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PRINT_DEBUG_HEX8(bpr);
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PRINT_DEBUG("\r\n");
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/* Set DRAM row page size register. */
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pci_write_config16(NB, RPS, rps);
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PRINT_DEBUG("RPS has been set to 0x");
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PRINT_DEBUG_HEX16(rps);
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PRINT_DEBUG("\r\n");
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/* ### ECC */
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pci_write_config8(NB, NBXCFG + 3, nbxecc);
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PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
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PRINT_DEBUG_HEX8(nbxecc);
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PRINT_DEBUG("\r\n");
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/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
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* TODO: Registered SDRAM support.
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*/
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edosd &= 0x07;
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if (edosd & 0x02) {
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edosd |= 0x00;
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} else if (edosd & 0x04) {
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edosd |= 0x08;
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}
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edosd &= 0x18;
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/* edosd is now in the form needed for DRAMC[4:3]. */
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value = pci_read_config8(NB, DRAMC) & 0xe7;
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value |= edosd;
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pci_write_config8(NB, DRAMC, value);
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PRINT_DEBUG("DRAMC has been set to 0x");
|
||||
PRINT_DEBUG_HEX8(value);
|
||||
PRINT_DEBUG("\r\n");
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(void)
|
||||
{
|
||||
/* TODO: Don't hardcode the values here, get info via SPD. */
|
||||
|
||||
/* Map all legacy regions to RAM (read/write). This is required if
|
||||
* you want to use the RAM area from 768 KB - 1 MB. If the PAM
|
||||
* registers are not set here appropriately, the RAM in that region
|
||||
* will not be accessible, thus a RAM check of it will also fail.
|
||||
*/
|
||||
pci_write_config8(NB, PAM0, 0x30);
|
||||
pci_write_config8(NB, PAM1, 0x33);
|
||||
pci_write_config8(NB, PAM2, 0x33);
|
||||
pci_write_config8(NB, PAM3, 0x33);
|
||||
pci_write_config8(NB, PAM4, 0x33);
|
||||
pci_write_config8(NB, PAM5, 0x33);
|
||||
pci_write_config8(NB, PAM6, 0x33);
|
||||
|
||||
/* TODO: Set DRB0-DRB7. */
|
||||
/* Currently this is hardcoded to one 64 MB DIMM in slot 0. */
|
||||
pci_write_config8(NB, DRB0, 0x08);
|
||||
pci_write_config8(NB, DRB1, 0x08);
|
||||
pci_write_config8(NB, DRB2, 0x08);
|
||||
pci_write_config8(NB, DRB3, 0x08);
|
||||
pci_write_config8(NB, DRB4, 0x08);
|
||||
pci_write_config8(NB, DRB5, 0x08);
|
||||
pci_write_config8(NB, DRB6, 0x08);
|
||||
pci_write_config8(NB, DRB7, 0x08);
|
||||
|
||||
/* TODO: Set DRAMC. Don't enable refresh for now. */
|
||||
pci_write_config8(NB, DRAMC, 0x08);
|
||||
|
||||
/* TODO: Set RPS. Needs to be fixed for multiple DIMM support. */
|
||||
pci_write_config16(NB, RPS, 0x0001);
|
||||
/* Setup DRAM row boundary registers and other attributes. */
|
||||
set_dram_row_attributes();
|
||||
|
||||
/* TODO: Set SDRAMC. */
|
||||
pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */
|
||||
|
||||
/* TODO: Set PGPOL. */
|
||||
// pci_write_config16(NB, PGPOL, 0x0107);
|
||||
pci_write_config16(NB, PGPOL, 0x0123);
|
||||
|
||||
/* TODO: Set NBXCFG. */
|
||||
// pci_write_config32(NB, NBXCFG, 0x0100220c); // FIXME?
|
||||
pci_write_config32(NB, NBXCFG, 0xff00800c);
|
||||
/* TODO */
|
||||
set_dram_buffer_strength();
|
||||
|
||||
/* TODO: Set PMCR? */
|
||||
// pci_write_config8(NB, PMCR, 0x14);
|
||||
pci_write_config8(NB, PMCR, 0x10);
|
||||
|
||||
/* TODO? */
|
||||
pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40);
|
||||
pci_write_config8(NB, DRAMT, 0x03);
|
||||
pci_write_config8(NB, MBSC, 0x03);
|
||||
pci_write_config8(NB, SCRR, 0x38);
|
||||
}
|
||||
|
||||
static void sdram_enable(void)
|
||||
|
|
Loading…
Reference in New Issue