Documentation: Add Asus P8Z77-M
Change-Id: I01f990408c4552b69c04e849e7faaf9f51f24a51 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Keith Hui
Felix Held
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# ASUS P8Z77-M
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This page describes how to run coreboot on the [ASUS P8Z77-M].
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## Flashing coreboot
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```eval_rst
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Model | W25Q64FVA1Q |
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+---------------------+----------------+
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| Size | 8 MiB |
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+---------------------+----------------+
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| Package | DIP-8 |
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+---------------------+----------------+
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| Socketed | yes |
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+---------------------+----------------+
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| Write protection | yes |
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+---------------------+----------------+
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| Dual BIOS feature | no |
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+---------------------+----------------+
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| Internal flashing | yes |
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+---------------------+----------------+
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```
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The flash chip is located between the blue SATA ports.
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The main SPI flash cannot be written internally because Asus disables BIOSWE and
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enables ``BLE/SMM_BWP`` flags in ``BIOS_CNTL`` for their latest bioses.
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To install coreboot for the first time, the flash chip must be removed and
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flashed with an external programmer; flashing in-circuit doesn't work.
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The flash chip is socketed, so it's easy to remove and reflash.
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## Working
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- All USB2 ports (mouse, keyboard and thumb drive)
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- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
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- Gigabit Ethernet (RTL8111F)
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- SATA3, SATA2 (all ports, hot-swap not tested)
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(Blue SATA2) (Blue SATA2) (White SATA3)
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port 5 port 3 port 1
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port 6 port 4 port 2
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- CPU Temp sensors and hardware monitor (some values don't make sense)
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- Native and MRC memory initialization
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(please see [Native raminit compatibility] and [MRC memory compatibility])
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- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
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(VGA/DVI-D/HDMI tested and working)
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- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3
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(Arch based))
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- Serial port
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- PCI slot
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Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested)
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Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from
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SeaBIOS)
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- S3 suspend from Linux
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- 2-channel analog audio (WAV playback by mplayer via back panel line out port)
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- Windows 10 with libgfxinit high resolution framebuffer and VBT
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## Known issues
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- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could
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be reconfigured by the blob.
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- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config.
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Otherwise integrated graphics would fail with a black screen.
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- PCI POST card is not functional because the PCI bridge early init is not yet done.
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- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for
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an x8, and is electrically an x4 only.
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## Untested
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- Wake-on-LAN
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- USB3 on header
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- TPM header
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- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
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- HDMI and S/PDIF audio out
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## Not working
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- PS/2 keyboard or mouse
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- 4 and 6 channel analog audio out: Rear left and right audio is a muted
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copy of front left and right audio, and the other two channels are silent.
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## Native (and MRC) raminit compatibility
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- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
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- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable
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with obvious pattern of bit errors during memtest86+ runs.
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- Samsung PC3-10600U 2x2GB kit works at full rated speed.
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- Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
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## Extra onboard buttons
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The board has two onboard buttons, and each has a related LED nearby.
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What controls the LEDs and what the buttons control are unknown,
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therefore they currently do nothing under coreboot.
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- BIOS_FLBK
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OEM firmware uses this button to facilitate a simple update mechanism
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via a USB drive plugged into the bottom USB port of the USB/LAN stack.
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- MemOK!
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OEM firmware uses this button for memory tuning related to overclocking.
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6779D |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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- [Flash chip datasheet][W25Q64FVA1Q]
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[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/
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[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
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[flashrom]: https://flashrom.org/Flashrom
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