Add WinBond Super IO helpers.
* These helpers severely clear up winbond superio usage. * Removed board_iwill_dk8_htx as it can be replaced by board_agami_aruma (Mondrian Nuessle). * Renamed board_agami_aruma to w83627hf_gpio24_raise. * Clarified comments in w83627hf_gpio24_raise, and added some things from the old iwill code. * Moved all board functions name argument to const. (warning breaks build) * Moved iwill entry in board_pciid_enables. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Luc Verhaegen
Peter Stuge
parent
7ea18cf5dd
commit
5941c25fe8
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@ -23,108 +23,87 @@
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#include "flash.h"
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#include "debug.h"
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static int board_iwill_dk8_htx(const char *name)
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{
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/* Extended function index register, either 0x2e or 0x4e. */
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#define EFIR 0x2e
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/* Extended function data register, one plus the index reg. */
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#define EFDR EFIR + 1
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char b;
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/* Disable the flash write protect (which is connected to the
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* Winbond W83627HF GPIOs).
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/*
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* Helper functions for many Winbond superIOs of the w836xx range.
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*/
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outb(0x87, EFIR); /* Sequence to unlock extended functions */
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outb(0x87, EFIR);
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#define W836_INDEX 0x2E
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#define W836_DATA 0x2F
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/* Activate logical device. */
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outb(0x7, EFIR);
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outb(8, EFDR);
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/* Enter extended functions */
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static void
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w836xx_ext_enter(void)
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{
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outb(0x87, W836_INDEX);
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outb(0x87, W836_INDEX);
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}
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/* Set GPIO regs. */
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outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */
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b = inb(EFDR) | 0xd0;
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outb(0x2b, EFIR);
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outb(b, EFDR);
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/* Leave extended functions */
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static void
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w836xx_ext_leave(void)
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{
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outb(0xAA, W836_INDEX);
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}
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outb(0x30, EFIR); /* GPIO2 */
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b = inb(EFDR) | 0x01;
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outb(0x30, EFIR);
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outb(b, EFDR);
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/* General functions for read/writing WB SuperIOs */
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static unsigned char
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wbsio_read(unsigned char index)
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{
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outb(index, W836_INDEX);
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return inb(W836_DATA);
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}
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outb(0xf0, EFIR); /* IO sel */
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b = inb(EFDR) | 0xef;
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outb(0xf0, EFIR);
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outb(b, EFDR);
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static void
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wbsio_write(unsigned char index, unsigned char data)
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{
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outb(index, W836_INDEX);
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outb(data, W836_DATA);
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}
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outb(0xf1, EFIR); /* GPIO data reg */
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b = inb(EFDR) | 0x16;
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outb(0xf1, EFIR);
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outb(b, EFDR);
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static void
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wbsio_mask(unsigned char index, unsigned char data,
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unsigned char mask)
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{
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unsigned char tmp;
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outb(0xf2, EFIR); /* GPIO inversion reg */
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b = inb(EFDR) | 0x00;
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outb(0xf2, EFIR);
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outb(b, EFDR);
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/* Lock extended functions again. */
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outb(0xaa, EFIR); /* Command to exit extended functions */
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return 0;
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outb(index, W836_INDEX);
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tmp = inb(W836_DATA) & ~mask;
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outb(tmp | (data & mask), W836_DATA);
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}
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/*
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* Match on pci-ids, no report received, just data from the mainboard
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* specific code:
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* main: 0x1022:0x746B, which is the SMBUS controller.
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* card: 0x1022:0x36C0...
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* WinBond w83627hf: raise GPIO24.
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*
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* Suited for:
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* * Agami Aruma
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* * IWILL DK8-HTX
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*/
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static int board_agami_aruma(char *name)
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static int w83627hf_gpio24_raise(const char *name)
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{
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/* Extended function index register, either 0x2e or 0x4e */
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#define EFIR 0x2e
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/* Extended function data register, one plus the index reg. */
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#define EFDR EFIR + 1
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char b;
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w836xx_ext_enter();
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/* Disable the flash write protect. The flash write protect is
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* connected to the WinBond w83627hf GPIO 24.
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*/
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outb(0x87, EFIR); /* sequence to unlock extended functions */
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outb(0x87, EFIR);
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outb(0x20, EFIR); /* SIO device ID register */
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b = inb(EFDR);
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printf_debug("\nW83627HF device ID = 0x%x\n",b);
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if (b != 0x52) {
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fprintf(stderr, "\nIncorrect device ID, aborting write protect disable\n");
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/* Is this the w83627hf? */
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if (wbsio_read(0x20) != 0x52) { /* SIO device ID register */
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fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(0x20));
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w836xx_ext_leave();
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return -1;
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}
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outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */
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b = inb(EFDR) | 0x10;
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outb(0x2b, EFIR);
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outb(b, EFDR); /* select GPIO 24 instead of WDTO */
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/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
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wbsio_mask(0x2B, 0x10, 0x10);
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outb(0x7, EFIR); /* logical device select */
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outb(0x8, EFDR); /* point to device 8, GPIO port 2 */
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wbsio_write(0x07, 0x08); /* Select logical device 8: GPIO port 2 */
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outb(0x30, EFIR); /* logic device activation control */
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outb(0x1, EFDR); /* activate */
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wbsio_mask(0x30, 0x01, 0x01); /* Activate logical device. */
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outb(0xf0, EFIR); /* GPIO 20-27 I/O selection register */
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b = inb(EFDR) & ~0x10;
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outb(0xf0, EFIR);
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outb(b, EFDR); /* set GPIO 24 as an output */
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wbsio_mask(0xF0, 0x00, 0x10); /* GPIO24 -> output */
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outb(0xf1, EFIR); /* GPIO 20-27 data register */
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b = inb(EFDR) | 0x10;
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outb(0xf1, EFIR);
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outb(b, EFDR); /* set GPIO 24 */
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wbsio_mask(0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
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outb(0xaa, EFIR); /* command to exit extended functions */
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wbsio_mask(0xF1, 0x10, 0x10); /* Raise GPIO24 */
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w836xx_ext_leave();
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return 0;
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}
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@ -135,7 +114,7 @@ static int board_agami_aruma(char *name)
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* We don't need to do this when using linuxbios, GPIO15 is never lowered there.
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*/
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static int board_via_epia_m(char *name)
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static int board_via_epia_m(const char *name)
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{
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struct pci_dev *dev;
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unsigned int base;
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@ -163,34 +142,12 @@ static int board_via_epia_m(char *name)
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return 0;
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}
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/*
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* Winbond LPC super IO.
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*
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* Raises the ROM MEMW# line.
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*/
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static void w83697_rom_memw_enable(void)
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{
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uint8_t val;
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outb(0x87, 0x2E); /* enable extended functions */
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outb(0x87, 0x2E);
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outb(0x24, 0x2E); /* rom bits live here */
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val = inb(0x2F);
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if (!(val & 0x02)) /* flash rom enabled? */
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outb(val | 0x08, 0x2F); /* enable MEMW# */
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outb(0xAA, 0x2E); /* disable extended functions */
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}
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/*
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* Suited for Asus A7V8X-MX SE and A7V400-MX.
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*
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*/
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static int board_asus_a7v8x_mx(char *name)
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static int board_asus_a7v8x_mx(const char *name)
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{
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struct pci_dev *dev;
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uint8_t val;
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@ -206,7 +163,13 @@ static int board_asus_a7v8x_mx(char *name)
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val &= 0x7F;
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pci_write_byte(dev, 0x59, val);
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w83697_rom_memw_enable();
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/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
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w836xx_ext_enter();
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if (!(wbsio_read(0x24) & 0x02)) /* flash rom enabled? */
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wbsio_mask(0x24, 0x08, 0x08); /* enable MEMW# */
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w836xx_ext_leave();
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return 0;
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}
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@ -241,18 +204,18 @@ struct board_pciid_enable {
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char *lb_part;
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char *name;
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int (*enable)(char *name);
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int (*enable)(const char *name);
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};
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struct board_pciid_enable board_pciid_enables[] = {
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{ 0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise },
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{ 0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
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"AGAMI", "ARUMA", "agami Aruma", board_agami_aruma },
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"AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise },
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{ 0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
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NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m },
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{ 0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
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NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx },
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{ 0x1022, 0x7468, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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"iwill", "dk8_htx", "IWILL DK8-HTX", board_iwill_dk8_htx },
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{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL } /* Keep this */
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};
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