diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e105061872..bc6c3db726 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -118,6 +118,12 @@ struct soc_intel_tigerlake_config {
 		L1_SS_L1_2,
 	} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
+	/* PCIe LTR: Enable (1) / Disable (0) */
+	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+
+	/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
+	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
+
 	/* SMBus */
 	uint8_t SmbusEnable;
 
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index ff6d3a978a..231399c676 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -122,10 +122,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* RP Configs */
-	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 		params->PcieRpL1Substates[i] =
 			get_l1_substate_control(config->PcieRpL1Substates[i]);
-
+		params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
+		params->PcieRpAdvancedErrorReporting[i] =
+			config->PcieRpAdvancedErrorReporting[i];
+	}
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
 	if (dev) {