GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

northbridge/amd/{lx,gx2}: remove immediate accesses of 0 

gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.

Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.

Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Patrick Georgi 2016-04-13 21:00:12 +02:00 committed by Martin Roth
parent fab8ae77cb
commit 59493717ad
4 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/gx2/northbridgeinit.c
View File

@ -656,7 +656,7 @@ void northbridge_init_early(void)
/* Now that the descriptor to memory is set up. */ /* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */ /* The memory controller needs one read to synch its lines before it can be used. */
i = *(volatile int *) 0; read32(zeroptr);
GeodeLinkPriority(); GeodeLinkPriority();

5
src/northbridge/amd/gx2/raminit.c
View File

@ -16,6 +16,7 @@
#include <cpu/amd/gx2def.h> #include <cpu/amd/gx2def.h>
#include <spd.h> #include <spd.h>
#include <stddef.h>
static const unsigned char NumColAddr[] = { static const unsigned char NumColAddr[] = {
0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
@ -596,10 +597,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* The RAM dll needs a write to lock on so generate a few dummy writes */ /* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */ /* Note: The descriptor needs to be enabled to point at memory */
volatile unsigned long *ptr;
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
ptr = (void *)i; write32(zeroptr + i, i);
*ptr = (unsigned long)i;
} }
printk(BIOS_INFO, "RAM DLL lock\n"); printk(BIOS_INFO, "RAM DLL lock\n");

2
src/northbridge/amd/lx/northbridgeinit.c
View File

@ -738,7 +738,7 @@ void northbridge_init_early(void)
/* Now that the descriptor to memory is set up. */ /* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */ /* The memory controller needs one read to synch its lines before it can be used. */
i = *(volatile int *)0; read32(zeroptr);
GeodeLinkPriority(); GeodeLinkPriority();

5
src/northbridge/amd/lx/raminit.c
View File

@ -18,6 +18,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <arch/io.h> #include <arch/io.h>
#include <spd.h> #include <spd.h>
#include <stddef.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include "raminit.h" #include "raminit.h"
#include "northbridge.h" #include "northbridge.h"
@ -747,10 +748,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* The RAM dll needs a write to lock on so generate a few dummy writes */ /* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */ /* Note: The descriptor needs to be enabled to point at memory */
volatile unsigned long *ptr;
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
ptr = (void *)i; write32(zeroptr + i, i);
*ptr = (unsigned long)i;
} }
/* SWAPSiF for PBZ 4112 (Errata 34) */ /* SWAPSiF for PBZ 4112 (Errata 34) */
/* check for failed DLL settings now that we have done a memory write. */ /* check for failed DLL settings now that we have done a memory write. */