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Kconfig whitespace fixes 

trivial whitespace fixes.  Mostly changing leading spaces to tabs.

Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2015-04-26 18:53:26 -06:00
parent 562d6f30a0
commit 595e7777e7
44 changed files with 164 additions and 164 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/Kconfig
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@ -56,14 +56,14 @@ config COMMON_CBFS_SPI_WRAPPER
Use common wrapper to interface CBFS to SPI bootrom. Use common wrapper to interface CBFS to SPI bootrom.
config MULTIPLE_CBFS_INSTANCES config MULTIPLE_CBFS_INSTANCES
bool "Multiple CBFS instances in the bootrom" bool "Multiple CBFS instances in the bootrom"
default n default n
depends on !ARCH_X86 depends on !ARCH_X86
help help
Account for the firmware image containing more than one CBFS Account for the firmware image containing more than one CBFS
instance. Locations of instances are known at build time and are instance. Locations of instances are known at build time and are
communicated between coreboot stages to make sure the next stage is communicated between coreboot stages to make sure the next stage is
loaded from the appropriate instance. loaded from the appropriate instance.
choice choice
prompt "Compiler to use" prompt "Compiler to use"
@ -317,8 +317,8 @@ source "src/arch/*/Kconfig"
source "src/vendorcode/*/Kconfig" source "src/vendorcode/*/Kconfig"
config SYSTEM_TYPE_LAPTOP config SYSTEM_TYPE_LAPTOP
default n default n
bool bool
menu "Chipset" menu "Chipset"
@ -578,7 +578,7 @@ config MAINBOARD_SERIAL_NUMBER
string "SMBIOS Serial Number" string "SMBIOS Serial Number"
depends on GENERATE_SMBIOS_TABLES depends on GENERATE_SMBIOS_TABLES
default "123456789" default "123456789"
help help
The Serial Number to store in SMBIOS structures. The Serial Number to store in SMBIOS structures.
config MAINBOARD_VERSION config MAINBOARD_VERSION

10
src/cpu/amd/agesa/family10/Kconfig
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@ -42,11 +42,11 @@ config XIP_ROM_SIZE
default 0x80000 default 0x80000
config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
default n default n
help help
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
Warning: Only enable this option when debuging or tracing AMD AGESA code. Warning: Only enable this option when debuging or tracing AMD AGESA code.
endif #CPU_AMD_AGESA_FAMILY10 endif #CPU_AMD_AGESA_FAMILY10

10
src/cpu/amd/agesa/family15/Kconfig
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@ -63,11 +63,11 @@ config XIP_ROM_SIZE
default 0x80000 default 0x80000
config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
default n default n
help help
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
Warning: Only enable this option when debuging or tracing AMD AGESA code. Warning: Only enable this option when debuging or tracing AMD AGESA code.
endif #CPU_AMD_AGESA_FAMILY15 endif #CPU_AMD_AGESA_FAMILY15

2
src/cpu/amd/socket_S1G1/Kconfig
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@ -1,5 +1,5 @@
config CPU_AMD_SOCKET_S1G1 config CPU_AMD_SOCKET_S1G1
bool bool
if CPU_AMD_SOCKET_S1G1 if CPU_AMD_SOCKET_S1G1

2
src/cpu/intel/socket_LGA771/Kconfig
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@ -1,6 +1,6 @@
config CPU_INTEL_SOCKET_LGA771 config CPU_INTEL_SOCKET_LGA771
bool bool
select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_6FX
select SSE2 select SSE2
select MMX select MMX
select AP_IN_SIPI_WAIT select AP_IN_SIPI_WAIT

4
src/drivers/intel/i210/Kconfig
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@ -1,3 +1,3 @@
config DRIVER_INTEL_I210 config DRIVER_INTEL_I210
bool bool
default n default n

4
src/drivers/ipmi/Kconfig
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@ -1,3 +1,3 @@
config IPMI_KCS config IPMI_KCS
bool bool
default n default n

4
src/drivers/lenovo/Kconfig
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@ -1,6 +1,6 @@
config DRIVERS_LENOVO_WACOM config DRIVERS_LENOVO_WACOM
bool bool
default n default n
if DRIVERS_LENOVO_WACOM if DRIVERS_LENOVO_WACOM

4
src/drivers/ricoh/rce822/Kconfig
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@ -1,3 +1,3 @@
config DRIVERS_RICOH_RCE822 config DRIVERS_RICOH_RCE822
bool bool
default n default n

4
src/mainboard/advansus/a785e-i/Kconfig
View File

@ -69,7 +69,7 @@ config IRQ_SLOT_COUNT
default 11 default 11
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "1002,9712" default "1002,9712"
endif #BOARD_ADVANSUS_A785E_I endif #BOARD_ADVANSUS_A785E_I

10
src/mainboard/amd/tilapia_fam10/Kconfig
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@ -57,12 +57,12 @@ config IRQ_SLOT_COUNT
default 11 default 11
config VGA_BIOS config VGA_BIOS
bool bool
default n default n
config VGA_BIOS_ID config VGA_BIOS_ID
string string
depends on VGA_BIOS depends on VGA_BIOS
default "1002,9615" default "1002,9615"
endif # BOARD_AMD_TILAPIA_FAM10 endif # BOARD_AMD_TILAPIA_FAM10

2
src/mainboard/aopen/Kconfig
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@ -1,7 +1,7 @@
if VENDOR_AOPEN if VENDOR_AOPEN
choice choice
prompt "Mainboard model" prompt "Mainboard model"
source "src/mainboard/aopen/*/Kconfig.name" source "src/mainboard/aopen/*/Kconfig.name"

4
src/mainboard/asus/m5a88-v/Kconfig
View File

@ -67,7 +67,7 @@ config IRQ_SLOT_COUNT
default 11 default 11
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "1002,9715" default "1002,9715"
endif #BOARD_ASUS_M5A88_V endif #BOARD_ASUS_M5A88_V

4
src/mainboard/avalue/eax-785e/Kconfig
View File

@ -69,7 +69,7 @@ config IRQ_SLOT_COUNT
default 11 default 11
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "1002,9712" default "1002,9712"
endif #BOARD_AVALUE_EAX_785E endif #BOARD_AVALUE_EAX_785E

2
src/mainboard/dmp/vortex86ex/Kconfig
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@ -187,7 +187,7 @@ config IDE_COMPATIBLE_SELECTION
depends on IDE_STANDARD_COMPATIBLE depends on IDE_STANDARD_COMPATIBLE
hex "IDE Compatible Selection" hex "IDE Compatible Selection"
default 0x808624db default 0x808624db
help help
IDE controller PCI vendor/device ID value setting. IDE controller PCI vendor/device ID value setting.
Higher 16-bit is vendor ID, lower 16-bit is device ID. Higher 16-bit is vendor ID, lower 16-bit is device ID.

36
src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
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@ -17,43 +17,43 @@ config BOARD_SPECIFIC_OPTIONS
select VGA select VGA
select INTEL_EDID select INTEL_EDID
select UDELAY_TSC select UDELAY_TSC
select SERIRQ_CONTINUOUS_MODE select SERIRQ_CONTINUOUS_MODE
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex
default 0xf0000000 default 0xf0000000
config DRAM_RESET_GATE_GPIO config DRAM_RESET_GATE_GPIO
int int
default 25 default 25
config USBDEBUG_HCD_INDEX config USBDEBUG_HCD_INDEX
int int
default 2 default 2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default gigabyte/ga-b75m-d3h default gigabyte/ga-b75m-d3h
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "GA-B75M-D3H" default "GA-B75M-D3H"
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int
default 18 default 18
config MAX_CPUS config MAX_CPUS
int int
default 8 default 8
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "8086,0162" default "8086,0162"
config VGA_BIOS_FILE config VGA_BIOS_FILE
string string
default "pci8086,0162.rom" default "pci8086,0162.rom"
config HAVE_IFD_BIN config HAVE_IFD_BIN
bool bool
@ -64,11 +64,11 @@ config HAVE_ME_BIN
default n default n
config IFD_BIOS_SECTION config IFD_BIOS_SECTION
string string
default "0x00600000:0x007fffff" default "0x00600000:0x007fffff"
config IFD_ME_SECTION config IFD_ME_SECTION
string string
default "0x00001000:0x004fffff" default "0x00001000:0x004fffff"
endif # BOARD_GIGABYTE_GA_B75M_D3H endif # BOARD_GIGABYTE_GA_B75M_D3H

36
src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
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@ -18,43 +18,43 @@ config BOARD_SPECIFIC_OPTIONS
select VGA select VGA
select INTEL_EDID select INTEL_EDID
select UDELAY_TSC select UDELAY_TSC
select SERIRQ_CONTINUOUS_MODE select SERIRQ_CONTINUOUS_MODE
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex
default 0xf8000000 default 0xf8000000
config DRAM_RESET_GATE_GPIO config DRAM_RESET_GATE_GPIO
int int
default 25 default 25
config USBDEBUG_HCD_INDEX config USBDEBUG_HCD_INDEX
int int
default 2 default 2
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default gigabyte/ga-b75m-d3v default gigabyte/ga-b75m-d3v
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "GA-B75M-D3V" default "GA-B75M-D3V"
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int
default 18 default 18
config MAX_CPUS config MAX_CPUS
int int
default 8 default 8
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "8086,0102" default "8086,0102"
config VGA_BIOS_FILE config VGA_BIOS_FILE
string string
default "pci8086,0102.rom" default "pci8086,0102.rom"
config HAVE_IFD_BIN config HAVE_IFD_BIN
bool bool
@ -65,11 +65,11 @@ config HAVE_ME_BIN
default n default n
config IFD_BIOS_SECTION config IFD_BIOS_SECTION
string string
default "0x00600000:0x007fffff" default "0x00600000:0x007fffff"
config IFD_ME_SECTION config IFD_ME_SECTION
string string
default "0x00001000:0x004fffff" default "0x00001000:0x004fffff"
endif # BOARD_GIGABYTE_GA_B75M_D3V endif # BOARD_GIGABYTE_GA_B75M_D3V

4
src/mainboard/google/urara/Kconfig
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@ -28,8 +28,8 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select SPI_FLASH_WINBOND select SPI_FLASH_WINBOND
select CPU_IMGTEC_PISTACHIO select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER select COMMON_CBFS_SPI_WRAPPER
select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_BOOTBLOCK_INIT
select SPI_FLASH select SPI_FLASH
config MAINBOARD_DIR config MAINBOARD_DIR

4
src/mainboard/google/veyron_brain/Kconfig
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@ -50,8 +50,8 @@ config MAINBOARD_VENDOR
default "Google" default "Google"
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_danger/Kconfig
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@ -50,8 +50,8 @@ config MAINBOARD_VENDOR
default "Google" default "Google"
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_jerry/Kconfig
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@ -61,8 +61,8 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
default 100 default 100
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_mighty/Kconfig
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@ -61,8 +61,8 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
default 100 default 100
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_pinky/Kconfig
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@ -61,8 +61,8 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
default 100 default 100
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_rialto/Kconfig
View File

@ -49,8 +49,8 @@ config MAINBOARD_VENDOR
default "Google" default "Google"
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

4
src/mainboard/google/veyron_speedy/Kconfig
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@ -61,8 +61,8 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
default 100 default 100
config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_BUS
int int
default 2 default 2
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

2
src/mainboard/hp/dl165_g6_fam10/Kconfig
View File

@ -1,7 +1,7 @@
if BOARD_HP_DL165_G6_FAM10 if BOARD_HP_DL165_G6_FAM10
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select CPU_AMD_SOCKET_F_1207 select CPU_AMD_SOCKET_F_1207
select NORTHBRIDGE_AMD_AMDFAM10 select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM21000

2
src/mainboard/supermicro/h8scm/Kconfig.name
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@ -1,2 +1,2 @@
config BOARD_SUPERMICRO_H8SCM config BOARD_SUPERMICRO_H8SCM
bool "H8SCM" bool "H8SCM"

4
src/mainboard/traverse/geos/Kconfig
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@ -26,7 +26,7 @@ config IRQ_SLOT_COUNT
default 6 default 6
config PLLMSRlo config PLLMSRlo
hex hex
default 0x00de602e default 0x00de602e
endif # BOARD_TRAVERSE_GEOS endif # BOARD_TRAVERSE_GEOS

2
src/mainboard/tyan/s8226/Kconfig.name
View File

@ -1,2 +1,2 @@
config BOARD_TYAN_S8226 config BOARD_TYAN_S8226
bool "S8226" bool "S8226"

10
src/northbridge/amd/amdfam10/Kconfig
View File

@ -58,8 +58,8 @@ config RAMTOP
default 0x400000 default 0x400000
config BOOTBLOCK_NORTHBRIDGE_INIT config BOOTBLOCK_NORTHBRIDGE_INIT
string string
default "northbridge/amd/amdfam10/bootblock.c" default "northbridge/amd/amdfam10/bootblock.c"
config SB_HT_CHAIN_UNITID_OFFSET_ONLY config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool bool
@ -112,9 +112,9 @@ endif
config SVI_HIGH_FREQ config SVI_HIGH_FREQ
bool bool
default n default n
help help
Select this for boards with a Voltage Regulator able to operate Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
menu "HyperTransport setup" menu "HyperTransport setup"
#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)

4
src/northbridge/amd/amdk8/Kconfig
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@ -58,8 +58,8 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
default n default n
config BOOTBLOCK_NORTHBRIDGE_INIT config BOOTBLOCK_NORTHBRIDGE_INIT
string string
default "northbridge/amd/amdk8/bootblock.c" default "northbridge/amd/amdk8/bootblock.c"
config SB_HT_CHAIN_UNITID_OFFSET_ONLY config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool bool

2
src/northbridge/amd/cimx/rd890/Kconfig
View File

@ -31,6 +31,6 @@ config REDIRECT_NBCIMX_TRACE_TO_SERIAL
This Option allows you to redirect the AMD Northbridge CIMX This Option allows you to redirect the AMD Northbridge CIMX
Trace debug information to the serial console. Trace debug information to the serial console.
Warning: Only enable this option when debuging or tracing AMD CIMX code. Warning: Only enable this option when debuging or tracing AMD CIMX code.
endif # NORTHBRIDGE_AMD_CIMX_RD890 endif # NORTHBRIDGE_AMD_CIMX_RD890

4
src/northbridge/amd/pi/Kconfig
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@ -18,8 +18,8 @@
# #
config NORTHBRIDGE_AMD_PI config NORTHBRIDGE_AMD_PI
bool bool
default CPU_AMD_PI default CPU_AMD_PI
select LATE_CBMEM_INIT select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_PI if NORTHBRIDGE_AMD_PI

36
src/northbridge/intel/i855/Kconfig
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@ -1,34 +1,34 @@
config NORTHBRIDGE_INTEL_I855 config NORTHBRIDGE_INTEL_I855
bool bool
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select LATE_CBMEM_INIT select LATE_CBMEM_INIT
choice choice
prompt "Onboard graphics" prompt "Onboard graphics"
default I855_VIDEO_MB_8MB default I855_VIDEO_MB_8MB
depends on NORTHBRIDGE_INTEL_I855 depends on NORTHBRIDGE_INTEL_I855
config I855_VIDEO_MB_OFF config I855_VIDEO_MB_OFF
bool "Disabled, 0KB" bool "Disabled, 0KB"
config I855_VIDEO_MB_1MB config I855_VIDEO_MB_1MB
bool "Enabled, 1MB" bool "Enabled, 1MB"
config I855_VIDEO_MB_4MB config I855_VIDEO_MB_4MB
bool "Enabled, 4MB" bool "Enabled, 4MB"
config I855_VIDEO_MB_8MB config I855_VIDEO_MB_8MB
bool "Enabled, 8MB" bool "Enabled, 8MB"
config I855_VIDEO_MB_16MB config I855_VIDEO_MB_16MB
bool "Enabled, 16MB" bool "Enabled, 16MB"
config I855_VIDEO_MB_32MB config I855_VIDEO_MB_32MB
bool "Enabled, 32MB" bool "Enabled, 32MB"
endchoice endchoice
config VIDEO_MB config VIDEO_MB
int int
default 0 if I855_VIDEO_MB_OFF default 0 if I855_VIDEO_MB_OFF
default 1 if I855_VIDEO_MB_1MB default 1 if I855_VIDEO_MB_1MB
default 4 if I855_VIDEO_MB_4MB default 4 if I855_VIDEO_MB_4MB
default 8 if I855_VIDEO_MB_8MB default 8 if I855_VIDEO_MB_8MB
default 16 if I855_VIDEO_MB_16MB default 16 if I855_VIDEO_MB_16MB
default 32 if I855_VIDEO_MB_32MB default 32 if I855_VIDEO_MB_32MB
depends on NORTHBRIDGE_INTEL_I855 depends on NORTHBRIDGE_INTEL_I855

18
src/southbridge/amd/cimx/sb800/Kconfig
View File

@ -27,8 +27,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
if SOUTHBRIDGE_AMD_CIMX_SB800 if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/amd/cimx/sb800/bootblock.c" default "southbridge/amd/cimx/sb800/bootblock.c"
config ENABLE_IDE_COMBINED_MODE config ENABLE_IDE_COMBINED_MODE
bool "Enable SATA IDE combined mode" bool "Enable SATA IDE combined mode"
@ -72,15 +72,15 @@ config SB800_SATA_RAID
endchoice endchoice
config SB800_SATA_MODE config SB800_SATA_MODE
hex hex
depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
default "0x0" if SB800_SATA_IDE default "0x0" if SB800_SATA_IDE
default "0x1" if SB800_SATA_RAID default "0x1" if SB800_SATA_RAID
default "0x2" if SB800_SATA_AHCI default "0x2" if SB800_SATA_AHCI
config SB_SUPERIO_HWM config SB_SUPERIO_HWM
bool bool
default n default n
if SB800_SATA_AHCI if SB800_SATA_AHCI
config AHCI_ROM_ID config AHCI_ROM_ID
@ -100,8 +100,8 @@ if SB800_SATA_RAID
config RAID_ROM_ID config RAID_ROM_ID
string "RAID device PCI IDs" string "RAID device PCI IDs"
default "1002,4393" default "1002,4393"
help help
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
config RAID_ROM_FILE config RAID_ROM_FILE
string "RAID ROM path and filename" string "RAID ROM path and filename"
@ -109,8 +109,8 @@ config RAID_ROM_FILE
default "site-local/sb800/raid.bin" default "site-local/sb800/raid.bin"
config RAID_MISC_ROM_FILE config RAID_MISC_ROM_FILE
string "RAID Misc ROM path and filename" string "RAID Misc ROM path and filename"
default "site-local/sb800/misc.bin" default "site-local/sb800/misc.bin"
depends on SB800_SATA_RAID depends on SB800_SATA_RAID
config RAID_MISC_ROM_POSITION config RAID_MISC_ROM_POSITION

24
src/southbridge/amd/cimx/sb900/Kconfig
View File

@ -29,30 +29,30 @@ config SATA_CONTROLLER_MODE
hex hex
default 0x0 default 0x0
help help
0x0 = Native IDE mode. 0x0 = Native IDE mode.
0x1 = RAID mode. 0x1 = RAID mode.
0x2 = AHCI mode. 0x2 = AHCI mode.
0x3 = Legacy IDE mode. 0x3 = Legacy IDE mode.
0x4 = IDE->AHCI mode. 0x4 = IDE->AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver). 0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE->AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
config PCIB_ENABLE config PCIB_ENABLE
bool bool
default n default n
help help
n = Disable PCI Bridge Device 14 Function 4. n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.
config ACPI_SCI_IRQ config ACPI_SCI_IRQ
hex hex
default 0x9 default 0x9
help help
Set SCI IRQ to 9. Set SCI IRQ to 9.
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/amd/cimx/sb900/bootblock.c" default "southbridge/amd/cimx/sb900/bootblock.c"
endif #SOUTHBRIDGE_AMD_CIMX_SB900 endif #SOUTHBRIDGE_AMD_CIMX_SB900

4
src/southbridge/amd/sb600/Kconfig
View File

@ -52,7 +52,7 @@ config SATA_MODE
default 0 if SATA_MODE_AHCI default 0 if SATA_MODE_AHCI
config HPET_MIN_TICKS config HPET_MIN_TICKS
hex hex
default 0x14 default 0x14
endif endif

4
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -79,9 +79,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1]. support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it WARNING: Never write a complete coreboot.rom to your flash ROM if it
was built with a fake IFD. It just won't work. was built with a fake IFD. It just won't work.
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION config IFD_BIOS_SECTION
depends on BUILD_WITH_FAKE_IFD depends on BUILD_WITH_FAKE_IFD

4
src/southbridge/intel/i3100/Kconfig
View File

@ -7,8 +7,8 @@ config SOUTHBRIDGE_INTEL_I3100
if SOUTHBRIDGE_INTEL_I3100 if SOUTHBRIDGE_INTEL_I3100
config HPET_MIN_TICKS config HPET_MIN_TICKS
hex hex
default 0x90 default 0x90
endif endif

2
src/southbridge/intel/i82801gx/Kconfig
View File

@ -34,7 +34,7 @@ config EHCI_BAR
default 0xfef00000 default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/i82801gx/bootblock.c" default "southbridge/intel/i82801gx/bootblock.c"
config HPET_MIN_TICKS config HPET_MIN_TICKS

2
src/southbridge/intel/i82801ix/Kconfig
View File

@ -40,7 +40,7 @@ config HPET_MIN_TICKS
default 0x80 default 0x80
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/i82801ix/bootblock.c" default "southbridge/intel/i82801ix/bootblock.c"
endif endif

4
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -69,9 +69,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1]. support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it WARNING: Never write a complete coreboot.rom to your flash ROM if it
was built with a fake IFD. It just won't work. was built with a fake IFD. It just won't work.
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION config IFD_BIOS_SECTION

4
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -71,9 +71,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1]. support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it WARNING: Never write a complete coreboot.rom to your flash ROM if it
was built with a fake IFD. It just won't work. was built with a fake IFD. It just won't work.
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION config IFD_BIOS_SECTION
depends on BUILD_WITH_FAKE_IFD depends on BUILD_WITH_FAKE_IFD

4
src/southbridge/intel/sch/Kconfig
View File

@ -47,8 +47,8 @@ config CMC_FILE
binary. binary.
config HPET_MIN_TICKS config HPET_MIN_TICKS
hex hex
default 0x80 default 0x80
endif endif