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soc/intel/alderlake: add power limits for Alder Lake-N SKUs 

This patch adds support for the ADL-N SKUs based on the PCH ID.
Document reference: 645548 (ADL-N EDS Volume 1).

BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board

Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Vidya Gopalakrishnan 2022-05-18 20:17:40 +05:30 committed by Paul Fagerburg
parent 60c519ee87
commit 596d5bc0fd
2 changed files with 26 additions and 0 deletions
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8
src/soc/intel/alderlake/chip.h
View File

@ -30,11 +30,15 @@ enum soc_intel_alderlake_power_limits {
ADL_M_282_15W_CORE, ADL_M_282_15W_CORE,
ADL_M_242_CORE, ADL_M_242_CORE,
ADL_P_442_45W_CORE, ADL_P_442_45W_CORE,
ADL_N_081_15W_CORE,
ADL_N_041_6W_CORE,
ADL_N_021_6W_CORE,
ADL_POWER_LIMITS_COUNT ADL_POWER_LIMITS_COUNT
}; };
/* TDP values for different SKUs */ /* TDP values for different SKUs */
enum soc_intel_alderlake_cpu_tdps { enum soc_intel_alderlake_cpu_tdps {
TDP_6W = 6,
TDP_9W = 9, TDP_9W = 9,
TDP_12W = 12, TDP_12W = 12,
TDP_15W = 15, TDP_15W = 15,
@ -61,6 +65,10 @@ static const struct {
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },
}; };
/* Types of display ports */ /* Types of display ports */

18
src/soc/intel/alderlake/chipset.cb
View File

@ -48,6 +48,24 @@ chip soc/intel/alderlake
.tdp_pl4 = 68, .tdp_pl4 = 68,
}" }"
register "power_limits_config[ADL_N_081_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 35,
.tdp_pl4 = 83,
}"
register "power_limits_config[ADL_N_041_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 25,
.tdp_pl4 = 78,
}"
register "power_limits_config[ADL_N_021_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 25,
.tdp_pl4 = 78,
}"
# NOTE: if any variant wants to override this value, use the same format # NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of # as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file. # putting it under register "common_soc_config" in overridetree.cb file.