From 59881a62c1100c6028919cca949e9736b9e44d6d Mon Sep 17 00:00:00 2001
From: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Date: Tue, 23 Feb 2021 17:52:14 +0800
Subject: [PATCH] mb/google/volteer/variants/drobit: Update DPTF parameters

Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern.

BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test image and verified by thermal team.

Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../volteer/variants/drobit/overridetree.cb   | 56 ++++++++++++++++++-
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index 608535e834..a29ce1c24b 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -16,8 +16,8 @@ chip soc/intel/tigerlake
 	register "tcc_offset" = "8"
 
 	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
-		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 51,
+		.tdp_pl1_override = 13,
+		.tdp_pl2_override = 28,
 		.tdp_pl4 = 105,
 	}"
 
@@ -69,6 +69,58 @@ chip soc/intel/tigerlake
 	}"
 
 	device domain 0 on
+                device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {.target = DPTF_TEMP_SENSOR_1,
+					       .thresholds = {TEMP_PCT(49, 90),
+							      TEMP_PCT(46, 80),
+							      TEMP_PCT(45, 70),
+							      TEMP_PCT(44, 65),
+							      TEMP_PCT(42, 57),
+							      TEMP_PCT(40, 50),}}}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,	       105, SHUTDOWN)}"
+
+				## Power Limits Control
+				# 13-17W PL1 in 125mW increments, avg over 28-32s interval
+				# PL2 is 28-64W, avg over 28-32s interval
+				register "controls.power_limits" = "{
+					.pl1 = {.min_power = 13000,
+						.max_power = 17000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 125,},
+					.pl2 = {.min_power = 28000,
+						.max_power = 64000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 500,}}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 5200, 220, 2200, },
+					[1] = {  80, 4900, 180, 1800, },
+					[2] = {  70, 4600, 145, 1450, },
+					[3] = {  60, 4200, 115, 1150, },
+					[4] = {  50, 3800,  90,  900, },
+					[5] = {  40, 3400,  55,  550, },
+					[6] = {  30, 2900,  30,  300, },
+					[7] = {  20, 2300,  15,  150, },
+					[8] = {  10, 1600,  10,  100, },
+					[9] = {   0,    0,   0,   50, }}"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF
+
 		device ref tbt_pcie_rp0 on
 			probe DB_USB USB4_GEN3
 		end