mb/google/octopus/var/fleex: Add ssfc codec cs42l42 support
Add cs42l42 codec support in fleex. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_CS42L42
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select DRIVERS_I2C_DA7219
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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@ -25,6 +25,7 @@
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#include <variant/gpio.h>
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extern struct chip_operations drivers_i2c_generic_ops;
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extern struct chip_operations drivers_i2c_cs42l42_ops;
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extern struct chip_operations drivers_i2c_da7219_ops;
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static bool is_cnvi_held_in_reset(void)
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@ -201,6 +202,13 @@ static void audio_codec_device_update(void)
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continue;
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}
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}
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if ((audio_dev->chip_ops == &drivers_i2c_cs42l42_ops) &&
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(codec == SSFC_AUDIO_CODEC_CS42L42)) {
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printk(BIOS_INFO, "enable CS42L42.\n");
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continue;
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}
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printk(BIOS_INFO, "%s has been disabled\n", audio_dev->chip_ops->name);
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audio_dev->enabled = 0;
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}
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@ -29,6 +29,7 @@ enum ssfc_audio_codec {
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SSFC_AUDIO_CODEC_DEFAULT,
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SSFC_AUDIO_CODEC_DA7219,
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SSFC_AUDIO_CODEC_RT5682,
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SSFC_AUDIO_CODEC_CS42L42,
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};
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#define SSFC_AUDIO_CODEC_OFFSET 9
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#define SSFC_AUDIO_CODEC_MASK 0x7
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@ -18,7 +18,8 @@ static const struct pad_config default_override_table[] = {
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PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),
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PAD_NC(GPIO_143, UP_20K),
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PAD_NC(GPIO_144, UP_20K),
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/* GPIO_144 -- Codec reset pin. */
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PAD_CFG_GPO(GPIO_144, 1, PWROK),
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PAD_NC(GPIO_145, UP_20K),
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/* EN_PP3300_TOUCHSCREEN */
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@ -135,6 +135,21 @@ chip soc/intel/apollolake
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/i2c/cs42l42
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)"
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register "ts_inv" = "true"
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register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
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register "ts_dbnc_fall" = "FALL_DEB_0_MS"
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register "btn_det_init_dbnce" = "100"
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register "btn_det_event_dbnce" = "10"
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register "bias_lvls[0]" = "15"
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register "bias_lvls[1]" = "8"
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register "bias_lvls[2]" = "4"
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register "bias_lvls[3]" = "1"
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register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
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device i2c 48 on end
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end
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end # - I2C 5
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device pci 17.2 on
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chip drivers/i2c/generic
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