mb/google/octopus/var/fleex: Add ssfc codec cs42l42 support

Add cs42l42 codec support in fleex.

BUG=b:184103445
TEST=boot to check cs42l42 is functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Eric Lai 2021-04-15 11:43:02 +08:00 committed by Tim Wawrzynczak
parent 411364564a
commit 598f2babdc
5 changed files with 27 additions and 1 deletions

View File

@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_CS42L42
select DRIVERS_I2C_DA7219
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID

View File

@ -25,6 +25,7 @@
#include <variant/gpio.h>
extern struct chip_operations drivers_i2c_generic_ops;
extern struct chip_operations drivers_i2c_cs42l42_ops;
extern struct chip_operations drivers_i2c_da7219_ops;
static bool is_cnvi_held_in_reset(void)
@ -201,6 +202,13 @@ static void audio_codec_device_update(void)
continue;
}
}
if ((audio_dev->chip_ops == &drivers_i2c_cs42l42_ops) &&
(codec == SSFC_AUDIO_CODEC_CS42L42)) {
printk(BIOS_INFO, "enable CS42L42.\n");
continue;
}
printk(BIOS_INFO, "%s has been disabled\n", audio_dev->chip_ops->name);
audio_dev->enabled = 0;
}

View File

@ -29,6 +29,7 @@ enum ssfc_audio_codec {
SSFC_AUDIO_CODEC_DEFAULT,
SSFC_AUDIO_CODEC_DA7219,
SSFC_AUDIO_CODEC_RT5682,
SSFC_AUDIO_CODEC_CS42L42,
};
#define SSFC_AUDIO_CODEC_OFFSET 9
#define SSFC_AUDIO_CODEC_MASK 0x7

View File

@ -18,7 +18,8 @@ static const struct pad_config default_override_table[] = {
PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),
PAD_NC(GPIO_143, UP_20K),
PAD_NC(GPIO_144, UP_20K),
/* GPIO_144 -- Codec reset pin. */
PAD_CFG_GPO(GPIO_144, 1, PWROK),
PAD_NC(GPIO_145, UP_20K),
/* EN_PP3300_TOUCHSCREEN */

View File

@ -135,6 +135,21 @@ chip soc/intel/apollolake
register "property_list[0].integer" = "1"
device i2c 1a on end
end
chip drivers/i2c/cs42l42
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)"
register "ts_inv" = "true"
register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
register "ts_dbnc_fall" = "FALL_DEB_0_MS"
register "btn_det_init_dbnce" = "100"
register "btn_det_event_dbnce" = "10"
register "bias_lvls[0]" = "15"
register "bias_lvls[1]" = "8"
register "bias_lvls[2]" = "4"
register "bias_lvls[3]" = "1"
register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
device i2c 48 on end
end
end # - I2C 5
device pci 17.2 on
chip drivers/i2c/generic