mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver
These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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4c1b6b31c0
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59962f3015
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@ -91,11 +91,7 @@ chip soc/intel/broadwell
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -91,11 +91,7 @@ chip soc/intel/broadwell
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -90,12 +90,8 @@ chip soc/intel/broadwell
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -92,11 +92,7 @@ chip soc/intel/broadwell
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -95,11 +95,7 @@ chip soc/intel/broadwell
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -135,11 +135,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -135,11 +135,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -128,11 +128,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -129,11 +129,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -142,11 +142,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -126,11 +126,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -142,11 +142,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -135,11 +135,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -135,11 +135,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -129,11 +129,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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@ -136,11 +136,7 @@ chip soc/intel/braswell
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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