mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver

These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.

Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.

Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/auron/variants/auron_paine/devicetree.cb

@@ -91,11 +91,7 @@ chip soc/intel/broadwell
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/auron/variants/auron_yuna/devicetree.cb

@@ -91,11 +91,7 @@ chip soc/intel/broadwell
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/auron/variants/gandof/devicetree.cb

@@ -91,11 +91,7 @@ chip soc/intel/broadwell
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/auron/variants/lulu/devicetree.cb

@@ -92,11 +92,7 @@ chip soc/intel/broadwell
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/auron/variants/samus/devicetree.cb

@@ -95,11 +95,7 @@ chip soc/intel/broadwell
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/banon/devicetree.cb

@@ -135,11 +135,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/celes/devicetree.cb

@@ -135,11 +135,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/cyan/devicetree.cb

@@ -128,11 +128,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/edgar/devicetree.cb

@@ -129,11 +129,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/kefka/devicetree.cb

@@ -142,11 +142,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/reks/devicetree.cb

@@ -126,11 +126,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/relm/devicetree.cb

@@ -142,11 +142,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/setzer/devicetree.cb

@@ -135,11 +135,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/terra/devicetree.cb

@@ -135,11 +135,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/ultima/devicetree.cb

@@ -129,11 +129,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

src/mainboard/google/cyan/variants/wizpig/devicetree.cb

@@ -136,11 +136,7 @@ chip soc/intel/braswell
 		device pci 1e.7 off end	# 8086 22ac -   SPI 3
 		device pci 1f.0 on	# 8086 229c - LPC bridge
 			chip drivers/pc80/tpm
-				# Rising edge interrupt
+				device pnp 0c31.0 on end
-				register "irq_polarity" = "2"
-				device pnp 0c31.0 on
-					irq 0x70 = 10
-				end
 			end
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end