mb/google/brya/var/banshee: Add mic mute switch setting
Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -174,6 +174,7 @@ config BOARD_GOOGLE_BANSHEE
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select MEMORY_SODIMM
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_GPIO_KEYS
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config BOARD_GOOGLE_CROTA
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bool "-> Crota"
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@ -186,7 +186,8 @@ static const struct pad_config override_gpio_table[] = {
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PAD_NC(GPP_F20, NONE),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* F22 : NC */
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/* F22 : NC ==> MIC_SW */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F22, NONE, DEEP),
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/* F23 : NC */
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/* H0 : GPPH0_BOOT_STRAP1 */
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@ -196,6 +196,17 @@ chip soc/intel/alderlake
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""MUTE""
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register "label" = ""mic_mute_switch""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F22)"
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register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED"
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register "key.dev_name" = ""MMSW""
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register "key.linux_code" = "SW_MUTE_DEVICE"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""mic_mute_switch_key""
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device generic 0 on end
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end
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end #I2C0
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device ref i2c1 on
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chip drivers/i2c/tpm
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