marvell/bg4cd: merge verstage into bootblock
If verified boot is enabled, merge verstage into bootblock. This also requires custom bootblock code to actually call into verstage. [pg: modified to match upstream] BUG=chrome-os-partner:32631 BRANCH=ToT TEST=booted on cosmos development board. Change-Id: I53251aac966ee15da24232c23fefa636de8b253b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45 Original-Reviewed-on: https://chromium-review.googlesource.com/229795 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_HARD_RESET
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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select MAINBOARD_HAS_CHROMEOS
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select RETURN_FROM_VERSTAGE
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select SOC_MARVELL_BG4CD
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select SPI_FLASH
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select SPI_FLASH_SPANSION
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@ -24,6 +24,7 @@ config SOC_MARVELL_BG4CD
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select ARCH_RAMSTAGE_ARMV7
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_VERSTAGE_ARMV7_M
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select ARM_BOOTBLOCK_CUSTOM if VBOOT2_VERIFY_FIRMWARE
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select BOOTBLOCK_CONSOLE
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select CPU_HAS_BOOTBLOCK_INIT
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select DYNAMIC_CBMEM
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@ -31,6 +32,7 @@ config SOC_MARVELL_BG4CD
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select GENERIC_UDELAY
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select HAVE_MONOTONIC_TIMER
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select GENERIC_GPIO_LIB
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select VERSTAGE_IN_BOOTBLOCK
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if SOC_MARVELL_BG4CD
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@ -17,6 +17,9 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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bootblock-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += bootblock_asm.S
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bootblock-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += bootblock.c
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bootblock-y += cbmem.c
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bootblock-y += i2c.c
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bootblock-y += monotonic_timer.c
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void main(void)
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{
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console_init();
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vboot2_verify_firmware();
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}
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <arch/asm.h>
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ENTRY(_start)
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr r0, =_stack
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ldr r1, =_estack
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ldr r2, =0xdeadbeef
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init_stack_loop:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne init_stack_loop
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call_verstage:
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ldr sp, =_estack /* Set up stack pointer */
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/*
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* we don't bl here to preserve lr so that we can return to the caller
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* of the bootblock
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*/
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b main
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ENDPROC(_start)
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@ -24,16 +24,22 @@
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SECTIONS
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{
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DRAM_START(0x00000000)
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RAMSTAGE(0x00200000, 128K)
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POSTRAM_CBFS_CACHE(0x01000000, 1M)
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SRAM_START(0x20000)
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SRAM_START(0x80000000)
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TTB(0x80000000, 16K)
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BOOTBLOCK(0x80004004, 16K - 4)
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VBOOT2_WORK(0x80008000, 16K)
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OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K)
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PRERAM_CBFS_CACHE(0x80016000, 4K)
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STACK(0x80017000, 4K)
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SRAM_END(0x80018000)
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BOOTBLOCK(0x20000, 40K)
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/* there is no VERSTAGE because it's built into bootblock */
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PRERAM_CBFS_CACHE(0x2A000, 8K)
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STACK(0x2C000, 8K)
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VBOOT2_WORK(0x2E000, 16K)
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SRAM_END(0x40000)
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DRAM_START(0x40000)
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RAMSTAGE(0x40000, 128K)
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POSTRAM_CBFS_CACHE(0x60000, 1M)
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ROMSTAGE(0xF7A40000, 32K)
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TTB(0xF7A48000, 16K)
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}
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