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Clean up Emerald Lake 2 mainboard directory 

Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Gabe Black 2012-03-30 14:33:02 -07:00 committed by Stefan Reinauer
parent 8172d0be97
commit 599e204efc
3 changed files with 6 additions and 6 deletions
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6
src/mainboard/intel/emeraldlake2/gpio.h
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@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_GPIO_H
#define LINK_GPIO_H
#ifndef EMERALDLAKE2_GPIO_H
#define EMERALDLAKE2_GPIO_H
#include "southbridge/intel/bd82x6x/gpio.h"
@ -84,7 +84,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = {
const struct pch_gpio_set3 pch_gpio_set3_level = {
};
const struct pch_gpio_map link_gpio_map = {
const struct pch_gpio_map emeraldlake2_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,

2
src/mainboard/intel/emeraldlake2/romstage.c
View File

@ -242,7 +242,7 @@ void main(unsigned long bist)
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&link_gpio_map);
setup_pch_gpios(&emeraldlake2_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */

4
src/mainboard/intel/emeraldlake2/thermal.h
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef LINK_THERMAL_H
#define LINK_THERMAL_H
#ifndef EMERALDLAKE2_THERMAL_H
#define EMERALDLAKE2_THERMAL_H
/* Fan is OFF */
#define FAN4_THRESHOLD_OFF 0