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mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place 

The preferred location for the SPD data on mc_ehl based boards is the
HW-Info data structure. Inside this structure there is a field of 128
bytes available for the SPD data. So in order to use it construct a
buffer in memory which is 256 bytes long (as FSP requests minimum 256
bytes for the SPD data) and where the upper 128 bytes are taken from
HW-Info holding the needed timing parameters for LPDDR4.
If there is a case where HW-Info is not accessible or where the
contained SPD data is not valid (by checking the CRC in HW-Info SPD)
fall back to fixed SPD data set in CBFS.

Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Werner Zeh 2021-10-07 16:12:06 +02:00 committed by Felix Held
parent bf766832c5
commit 59a8355e5f
1 changed files with 22 additions and 3 deletions
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25
src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
View File

@ -1,20 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/mmio.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <console/console.h>
#include <device/dram/common.h>
#include <hwilib.h>
#include <soc/meminit.h> #include <soc/meminit.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <string.h>
#include <types.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)
{ {
static struct spd_info spd_info; static struct spd_info spd_info;
const struct mb_cfg *board_cfg = variant_memcfg_config(); const struct mb_cfg *board_cfg = variant_memcfg_config();
static uint8_t spd_data[0x100];
const char *cbfs_hwi_name = "hwinfo.hex";
/* TODO: Read the resistor strap to get number of memory segments */ /* TODO: Read the resistor strap to get number of memory segments */
bool half_populated = false; bool half_populated = false;
/* Initialize spd information for LPDDR4x board */
spd_info.read_type = READ_SPD_CBFS;
spd_info.spd_spec.spd_index = 0x00;
/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
memset(spd_data, 0, sizeof(spd_data));
if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
(hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
(ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data);
spd_info.read_type = READ_SPD_MEMPTR;
} else {
printk(BIOS_WARNING, "SPD in HW-Info not valid, fall back to spd.bin!\n");
spd_info.read_type = READ_SPD_CBFS;
spd_info.spd_spec.spd_index = 0x00;
}
/* Initialize variant specific configurations */ /* Initialize variant specific configurations */
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
} }